From a8d3a68971ccc4e47c54a906aae374a9a54b1415 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 23 Jul 2014 08:40:31 +0200
Subject: Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor --
 step 2/3

---
 passes/techmap/extract.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'passes/techmap/extract.cc')

diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index 5a729808..988917b1 100644
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -315,7 +315,7 @@ namespace
 			RTLIL::Wire *wire = it.second;
 			if (wire->port_id > 0) {
 				for (int i = 0; i < wire->width; i++)
-					sig2port.insert(sigmap(RTLIL::SigSpec(wire, 1, i)), std::pair<std::string, int>(wire->name, i));
+					sig2port.insert(sigmap(RTLIL::SigSpec::grml(wire, i)), std::pair<std::string, int>(wire->name, i));
 				cell->connections[wire->name] = RTLIL::SigSpec(RTLIL::State::Sz, wire->width);
 			}
 		}
-- 
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