From e6d33513a5b809facc6e3e5e75d2248bfa94f82b Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 31 Jul 2014 14:11:39 +0200
Subject: Added module->design and cell->module, wire->module pointers

---
 passes/techmap/extract.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'passes/techmap/extract.cc')

diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index ed389f2f..060a8740 100644
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -724,7 +724,7 @@ struct ExtractPass : public Pass {
 
 				RTLIL::Module *newMod = new RTLIL::Module;
 				newMod->name = stringf("\\needle%05d_%s_%dx", needleCounter++, id2cstr(haystack_map.at(result.graphId)->name), result.totalMatchesAfterLimits);
-				map->modules_[newMod->name] = newMod;
+				map->add(newMod);
 
 				int portCounter = 1;
 				for (auto wire : wires) {
-- 
cgit v1.2.3