From d68c993ed2ea384db4d6af5161b3b36096828499 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 21:16:05 +0200 Subject: Changed more code to the new RTLIL::Wire constructors --- passes/techmap/iopadmap.cc | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) (limited to 'passes/techmap/iopadmap.cc') diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc index 114d28e2..ab3bb3ed 100644 --- a/passes/techmap/iopadmap.cc +++ b/passes/techmap/iopadmap.cc @@ -164,13 +164,8 @@ struct IopadmapPass : public Pass { log("Mapping port %s.%s using %s.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name), celltype.c_str()); RTLIL::Wire *new_wire = NULL; - if (!portname2.empty()) { - new_wire = new RTLIL::Wire; - *new_wire = *wire; - wire->name = NEW_ID; - module->wires[wire->name] = wire; - module->wires[new_wire->name] = new_wire; - } + if (!portname2.empty()) + new_wire = module->addWire(NEW_ID, wire); if (flag_bits) { -- cgit v1.2.3