From 1bf7a18fec76cf46a5b8710a75371e23b68d147d Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 14 Aug 2014 16:13:42 +0200
Subject: Added module->ports

---
 passes/abc/blifparse.cc       | 3 +--
 passes/hierarchy/hierarchy.cc | 2 ++
 passes/hierarchy/submod.cc    | 7 +++----
 passes/techmap/extract.cc     | 4 ++--
 4 files changed, 8 insertions(+), 8 deletions(-)

(limited to 'passes')

diff --git a/passes/abc/blifparse.cc b/passes/abc/blifparse.cc
index 1891a745..bc8f343a 100644
--- a/passes/abc/blifparse.cc
+++ b/passes/abc/blifparse.cc
@@ -58,7 +58,6 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name)
 	RTLIL::Const *lutptr = NULL;
 	RTLIL::State lut_default_state = RTLIL::State::Sx;
 
-	int port_count = 0;
 	module->name = "\\netlist";
 	design->add(module);
 
@@ -91,6 +90,7 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name)
 				continue;
 
 			if (!strcmp(cmd, ".end")) {
+				module->fixup_ports();
 				free(buffer);
 				return design;
 			}
@@ -99,7 +99,6 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name)
 				char *p;
 				while ((p = strtok(NULL, " \t\r\n")) != NULL) {
 					RTLIL::Wire *wire = module->addWire(stringf("\\%s", p));
-					wire->port_id = ++port_count;
 					if (!strcmp(cmd, ".inputs"))
 						wire->port_input = true;
 					else
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 50b4989d..2f28afb2 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -126,6 +126,8 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
 			wire->port_output = decl.output;
 		}
 
+		mod->fixup_ports();
+
 		for (auto &para : parameters)
 			log("  ignoring parameter %s.\n", RTLIL::id2cstr(para));
 
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc
index 89f45e02..1b03ab55 100644
--- a/passes/hierarchy/submod.cc
+++ b/passes/hierarchy/submod.cc
@@ -106,7 +106,7 @@ struct SubmodWorker
 		RTLIL::Module *new_mod = new RTLIL::Module;
 		new_mod->name = submod.full_name;
 		design->add(new_mod);
-		int port_counter = 1, auto_name_counter = 1;
+		int auto_name_counter = 1;
 
 		std::set<RTLIL::IdString> all_wire_names;
 		for (auto &it : wire_flags) {
@@ -151,9 +151,6 @@ struct SubmodWorker
 			new_wire->start_offset = wire->start_offset;
 			new_wire->attributes = wire->attributes;
 
-			if (new_wire->port_input || new_wire->port_output)
-				new_wire->port_id = port_counter++;
-
 			if (new_wire->port_input && new_wire->port_output)
 				log("  signal %s: inout %s\n", wire->name.c_str(), new_wire->name.c_str());
 			else if (new_wire->port_input)
@@ -166,6 +163,8 @@ struct SubmodWorker
 			flags.new_wire = new_wire;
 		}
 
+		new_mod->fixup_ports();
+
 		for (RTLIL::Cell *cell : submod.cells) {
 			RTLIL::Cell *new_cell = new_mod->addCell(cell->name, cell);
 			for (auto &conn : new_cell->connections_)
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index 985d51e5..ebf4d77f 100644
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -726,14 +726,14 @@ struct ExtractPass : public Pass {
 				newMod->name = stringf("\\needle%05d_%s_%dx", needleCounter++, id2cstr(haystack_map.at(result.graphId)->name), result.totalMatchesAfterLimits);
 				map->add(newMod);
 
-				int portCounter = 1;
 				for (auto wire : wires) {
 					RTLIL::Wire *newWire = newMod->addWire(wire->name, wire->width);
-					newWire->port_id = portCounter++;
 					newWire->port_input = true;
 					newWire->port_output = true;
 				}
 
+				newMod->fixup_ports();
+
 				for (auto cell : cells) {
 					RTLIL::Cell *newCell = newMod->addCell(cell->name, cell->type);
 					newCell->parameters = cell->parameters;
-- 
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