From 236fc4209c17bf96b37e6f8a29a8aa3f24d5df45 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 20 Feb 2014 23:30:15 +0100 Subject: Added "extract -map %" --- passes/techmap/extract.cc | 40 ++++++++++++++++++++++++++++++---------- 1 file changed, 30 insertions(+), 10 deletions(-) (limited to 'passes') diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index eff14ff0..06b0df2d 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -315,6 +315,10 @@ struct ExtractPass : public Pass { log(" use the modules in this file as reference. This option can be used\n"); log(" multiple times.\n"); log("\n"); + log(" -map %%\n"); + log(" use the modules in this in-memory design as reference. This option can\n"); + log(" be used multiple times.\n"); + log("\n"); log(" -verbose\n"); log(" print debug output while analyzing\n"); log("\n"); @@ -524,16 +528,32 @@ struct ExtractPass : public Pass { if (!mine_mode) { map = new RTLIL::Design; - for (auto &filename : map_filenames) { - FILE *f = fopen(filename.c_str(), "rt"); - if (f == NULL) - log_cmd_error("Can't open map file `%s'.\n", filename.c_str()); - Frontend::frontend_call(map, f, filename, (filename.size() > 3 && filename.substr(filename.size()-3) == ".il") ? "ilang" : "verilog"); - fclose(f); - - if (filename.size() <= 3 || filename.substr(filename.size()-3) != ".il") { - Pass::call(map, "proc"); - Pass::call(map, "opt_clean"); + for (auto &filename : map_filenames) + { + if (filename.substr(0, 1) == "%") + { + if (!saved_designs.count(filename.substr(1))) { + delete map; + log_cmd_error("Can't saved design `%s'.\n", filename.c_str()+1); + } + for (auto &it : saved_designs.at(filename.substr(1))->modules) + if (!map->modules.count(it.first)) + map->modules[it.first] = it.second->clone(); + } + else + { + FILE *f = fopen(filename.c_str(), "rt"); + if (f == NULL) { + delete map; + log_cmd_error("Can't open map file `%s'.\n", filename.c_str()); + } + Frontend::frontend_call(map, f, filename, (filename.size() > 3 && filename.substr(filename.size()-3) == ".il") ? "ilang" : "verilog"); + fclose(f); + + if (filename.size() <= 3 || filename.substr(filename.size()-3) != ".il") { + Pass::call(map, "proc"); + Pass::call(map, "opt_clean"); + } } } } -- cgit v1.2.3