From 5826670009e1018734de49aaf1554cb8a43d09d7 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 25 Jul 2014 14:23:31 +0200
Subject: Various RTLIL::SigSpec related code cleanups

---
 passes/cmds/show.cc | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'passes')

diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc
index 0a1d584c..8ff06899 100644
--- a/passes/cmds/show.cc
+++ b/passes/cmds/show.cc
@@ -171,13 +171,13 @@ struct ShowWorker
 
 	std::string gen_signode_simple(RTLIL::SigSpec sig, bool range_check = true)
 	{
-		if (sig.chunks().size() == 0) {
+		if (SIZE(sig) == 0) {
 			fprintf(f, "v%d [ label=\"\" ];\n", single_idx_count);
 			return stringf("v%d", single_idx_count++);
 		}
 
-		if (sig.chunks().size() == 1) {
-			const RTLIL::SigChunk &c = sig.chunks().front();
+		if (sig.is_chunk()) {
+			const RTLIL::SigChunk &c = sig.as_chunk();
 			if (c.wire != NULL && design->selected_member(module->name, c.wire->name)) {
 				if (!range_check || c.wire->width == c.width)
 						return stringf("n%d", id2num(c.wire->name));
-- 
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