From b64b38eea2e9a7de30d6045f069c86bf4446134f Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 15 Aug 2014 14:18:40 +0200
Subject: Renamed $lut ports to follow A-Y naming scheme

---
 passes/abc/blifparse.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'passes')

diff --git a/passes/abc/blifparse.cc b/passes/abc/blifparse.cc
index bc8f343a..1fbb5720 100644
--- a/passes/abc/blifparse.cc
+++ b/passes/abc/blifparse.cc
@@ -195,8 +195,8 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name)
 				RTLIL::Cell *cell = module->addCell(NEW_ID, "$lut");
 				cell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.size());
 				cell->parameters["\\LUT"] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.size());
-				cell->setPort("\\I", input_sig);
-				cell->setPort("\\O", output_sig);
+				cell->setPort("\\A", input_sig);
+				cell->setPort("\\Y", output_sig);
 				lutptr = &cell->parameters.at("\\LUT");
 				lut_default_state = RTLIL::State::Sx;
 				continue;
-- 
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