From b9bd22b8c8d46284fba4d4c1cbd09092a9ccc5c3 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 2 Aug 2014 13:11:01 +0200 Subject: More cleanups related to RTLIL::IdString usage --- passes/cmds/connwrappers.cc | 6 ++--- passes/cmds/show.cc | 24 +++++++++++--------- passes/cmds/splice.cc | 8 +++---- passes/cmds/splitnets.cc | 2 +- passes/fsm/fsm_detect.cc | 2 +- passes/fsm/fsm_export.cc | 2 +- passes/fsm/fsm_extract.cc | 4 ++-- passes/hierarchy/hierarchy.cc | 30 ++++++++++++------------- passes/hierarchy/submod.cc | 10 ++++----- passes/memory/memory_collect.cc | 8 +++---- passes/memory/memory_map.cc | 4 ++-- passes/memory/memory_unpack.cc | 6 ++--- passes/opt/opt_clean.cc | 7 +++--- passes/opt/opt_const.cc | 42 +++++++++++++++++----------------- passes/opt/opt_rmdff.cc | 2 +- passes/opt/opt_share.cc | 8 +++---- passes/proc/proc_clean.cc | 2 +- passes/sat/eval.cc | 2 +- passes/sat/expose.cc | 50 ++++++++++++++++++++--------------------- passes/sat/sat.cc | 6 ++--- passes/sat/share.cc | 4 ++-- passes/techmap/dfflibmap.cc | 4 ++-- passes/techmap/extract.cc | 30 ++++++++++++------------- passes/techmap/simplemap.cc | 6 ++--- passes/techmap/techmap.cc | 36 ++++++++++++++--------------- passes/tests/test_autotb.cc | 44 ++++++++++++++++++------------------ 26 files changed, 176 insertions(+), 173 deletions(-) (limited to 'passes') diff --git a/passes/cmds/connwrappers.cc b/passes/cmds/connwrappers.cc index 5125ff5e..aac11716 100644 --- a/passes/cmds/connwrappers.cc +++ b/passes/cmds/connwrappers.cc @@ -30,8 +30,8 @@ struct ConnwrappersWorker bool is_signed; }; - std::set decl_celltypes; - std::map, portdecl_t> decls; + std::set decl_celltypes; + std::map, portdecl_t> decls; void add_port(std::string celltype, std::string portname, std::string widthparam, std::string signparam) { @@ -76,7 +76,7 @@ struct ConnwrappersWorker for (auto &conn : cell->connections()) { - std::pair key(cell->type, conn.first); + std::pair key(cell->type, conn.first); if (!decls.count(key)) continue; diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index a2dd8051..bbc0ff44 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -111,7 +111,7 @@ struct ShowWorker return stringf("style=\"setlinewidth(3)\", label=\"<%d>\"", bits); } - const char *findColor(std::string member_name) + const char *findColor(RTLIL::IdString member_name) { for (auto &s : color_selections) if (s.second.selected_member(module->name, member_name)) { @@ -121,20 +121,22 @@ struct ShowWorker return ""; } - const char *findLabel(std::string member_name) + const char *findLabel(RTLIL::IdString member_name) { for (auto &s : label_selections) - if (s.second.selected_member(module->name, RTLIL::escape_id(member_name))) + if (s.second.selected_member(module->name, member_name)) return escape(s.first); return escape(member_name, true); } - const char *escape(std::string id, bool is_name = false) + const char *escape(RTLIL::IdString id, bool is_name = false) { - if (id.size() == 0) + std::string id_str = id.str(); + + if (id_str.size() == 0) return ""; - if (id[0] == '$' && is_name) { + if (id_str[0] == '$' && is_name) { if (enumerateIds) { if (autonames.count(id) == 0) { autonames[id] = autonames.size() + 1; @@ -142,17 +144,17 @@ struct ShowWorker } id = stringf("_%d_", autonames[id]); } else if (abbreviateIds) { - const char *p = id.c_str(); + const char *p = id_str.c_str(); const char *q = strrchr(p, '$'); - id = std::string(q); + id_str = std::string(q); } } - if (id[0] == '\\') - id = id.substr(1); + if (id_str[0] == '\\') + id_str = id_str.substr(1); std::string str; - for (char ch : id) { + for (char ch : id_str) { if (ch == '\\' || ch == '"') str += "\\"; str += ch; diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc index 07c6150c..ca71f7d8 100644 --- a/passes/cmds/splice.cc +++ b/passes/cmds/splice.cc @@ -33,8 +33,8 @@ struct SpliceWorker bool sel_by_wire; bool sel_any_bit; bool no_outputs; - std::set ports; - std::set no_ports; + std::set ports; + std::set no_ports; CellTypes ct; SigMap sigmap; @@ -224,7 +224,7 @@ struct SpliceWorker for (auto &it : rework_wires) { - std::string orig_name = it.first->name; + RTLIL::IdString orig_name = it.first->name; module->rename(it.first, NEW_ID); RTLIL::Wire *new_port = module->addWire(orig_name, it.first); @@ -283,7 +283,7 @@ struct SplicePass : public Pass { bool sel_by_wire = false; bool sel_any_bit = false; bool no_outputs = false; - std::set ports, no_ports; + std::set ports, no_ports; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc index 6b1dbe13..a3daf239 100644 --- a/passes/cmds/splitnets.cc +++ b/passes/cmds/splitnets.cc @@ -28,7 +28,7 @@ struct SplitnetsWorker void append_wire(RTLIL::Module *module, RTLIL::Wire *wire, int offset, int width, std::string format) { - std::string new_wire_name = wire->name; + std::string new_wire_name = wire->name.str(); if (format.size() > 0) new_wire_name += format.substr(0, 1); diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index 6025de15..5675dff5 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -26,7 +26,7 @@ static RTLIL::Module *module; static SigMap assign_map; -typedef std::pair sig2driver_entry_t; +typedef std::pair sig2driver_entry_t; static SigSet sig2driver, sig2user; static std::set muxtree_cells; static SigPool sig_at_port; diff --git a/passes/fsm/fsm_export.cc b/passes/fsm/fsm_export.cc index f6f9faa9..97ccf91e 100644 --- a/passes/fsm/fsm_export.cc +++ b/passes/fsm/fsm_export.cc @@ -62,7 +62,7 @@ void write_kiss2(struct RTLIL::Module *module, struct RTLIL::Cell *cell, std::st } else { kiss_name.assign(module->name); - kiss_name.append('-' + cell->name + ".kiss2"); + kiss_name.append('-' + cell->name.str() + ".kiss2"); } log("\n"); diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index cf2075fb..5e71c1f0 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -31,7 +31,7 @@ static RTLIL::Module *module; static SigMap assign_map; -typedef std::pair sig2driver_entry_t; +typedef std::pair sig2driver_entry_t; static SigSet sig2driver, sig2trigger; static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL::SigSpec &ctrl, std::map &states, RTLIL::Const *reset_state = NULL) @@ -277,7 +277,7 @@ static void extract_fsm(RTLIL::Wire *wire) fsm_cell->parameters["\\ARST_POLARITY"] = RTLIL::Const(arst_polarity ? 1 : 0, 1); fsm_cell->setPort("\\CTRL_IN", ctrl_in); fsm_cell->setPort("\\CTRL_OUT", ctrl_out); - fsm_cell->parameters["\\NAME"] = RTLIL::Const(wire->name); + fsm_cell->parameters["\\NAME"] = RTLIL::Const(wire->name.str()); fsm_cell->attributes = wire->attributes; fsm_data.copy_to_cell(fsm_cell); diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 67b57a94..28b4ad99 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -35,7 +35,7 @@ namespace { static void generate(RTLIL::Design *design, const std::vector &celltypes, const std::vector &portdecls) { - std::set found_celltypes; + std::set found_celltypes; for (auto i1 : design->modules_) for (auto i2 : i1.second->cells_) @@ -52,9 +52,9 @@ static void generate(RTLIL::Design *design, const std::vector &cell for (auto &celltype : found_celltypes) { - std::set portnames; - std::set parameters; - std::map portwidths; + std::set portnames; + std::set parameters; + std::map portwidths; log("Generate module for cell type %s:\n", celltype.c_str()); for (auto i1 : design->modules_) @@ -94,7 +94,7 @@ static void generate(RTLIL::Design *design, const std::vector &cell } while (portnames.size() > 0) { - std::string portname = *portnames.begin(); + RTLIL::IdString portname = *portnames.begin(); for (auto &decl : portdecls) if (decl.index == 0 && !fnmatch(decl.portname.c_str(), RTLIL::unescape_id(portname).c_str(), FNM_NOESCAPE)) { generate_port_decl_t d = decl; @@ -144,20 +144,20 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla RTLIL::Cell *cell = cell_it.second; if (cell->type.substr(0, 7) == "$array:") { - int pos_idx = cell->type.find_first_of(':'); - int pos_num = cell->type.find_first_of(':', pos_idx + 1); - int pos_type = cell->type.find_first_of(':', pos_num + 1); - int idx = atoi(cell->type.substr(pos_idx + 1, pos_num).c_str()); - int num = atoi(cell->type.substr(pos_num + 1, pos_type).c_str()); + int pos_idx = cell->type.str().find_first_of(':'); + int pos_num = cell->type.str().find_first_of(':', pos_idx + 1); + int pos_type = cell->type.str().find_first_of(':', pos_num + 1); + int idx = atoi(cell->type.str().substr(pos_idx + 1, pos_num).c_str()); + int num = atoi(cell->type.str().substr(pos_num + 1, pos_type).c_str()); array_cells[cell] = std::pair(idx, num); - cell->type = cell->type.substr(pos_type + 1); + cell->type = cell->type.str().substr(pos_type + 1); } if (design->modules_.count(cell->type) == 0) { - if (design->modules_.count("$abstract" + cell->type)) + if (design->modules_.count("$abstract" + cell->type.str())) { - cell->type = design->modules_.at("$abstract" + cell->type)->derive(design, cell->parameters); + cell->type = design->modules_.at("$abstract" + cell->type.str())->derive(design, cell->parameters); cell->parameters.clear(); did_something = true; continue; @@ -220,7 +220,7 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla for (auto &conn : cell->connections_) { int conn_size = conn.second.size(); - std::string portname = conn.first; + RTLIL::IdString portname = conn.first; if (portname.substr(0, 1) == "$") { int port_id = atoi(portname.substr(1).c_str()); for (auto &wire_it : mod->wires_) @@ -447,7 +447,7 @@ struct HierarchyPass : public Pass { bool did_something_once = false; while (did_something) { did_something = false; - std::vector modnames; + std::vector modnames; modnames.reserve(design->modules_.size()); for (auto &mod_it : design->modules_) modnames.push_back(mod_it.first); diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index 2a47002e..89f45e02 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -108,7 +108,7 @@ struct SubmodWorker design->add(new_mod); int port_counter = 1, auto_name_counter = 1; - std::set all_wire_names; + std::set all_wire_names; for (auto &it : wire_flags) { all_wire_names.insert(it.first->name); } @@ -134,7 +134,7 @@ struct SubmodWorker if (flags.is_int_driven && flags.is_ext_driven) new_wire_port_input = true, new_wire_port_output = true; - std::string new_wire_name = wire->name; + std::string new_wire_name = wire->name.str(); if (new_wire_port_input || new_wire_port_output) { while (new_wire_name[0] == '$') { std::string next_wire_name = stringf("\\n%d", auto_name_counter++); @@ -228,7 +228,7 @@ struct SubmodWorker if (submodules.count(submod_str) == 0) { submodules[submod_str].name = submod_str; - submodules[submod_str].full_name = module->name + "_" + submod_str; + submodules[submod_str].full_name = module->name.str() + "_" + submod_str; while (design->modules_.count(submodules[submod_str].full_name) != 0 || module->count_id(submodules[submod_str].full_name) != 0) submodules[submod_str].full_name += "_"; @@ -306,12 +306,12 @@ struct SubmodPass : public Pass { Pass::call(design, "opt_clean"); log_header("Continuing SUBMOD pass.\n"); - std::set handled_modules; + std::set handled_modules; bool did_something = true; while (did_something) { did_something = false; - std::vector queued_modules; + std::vector queued_modules; for (auto &mod_it : design->modules_) if (handled_modules.count(mod_it.first) == 0 && design->selected_whole_module(mod_it.first)) queued_modules.push_back(mod_it.first); diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index 8887d195..471a7d53 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -62,7 +62,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) for (auto &cell_it : module->cells_) { RTLIL::Cell *cell = cell_it.second; - if ((cell->type == "$memwr" || cell->type == "$memrd") && cell->parameters["\\MEMID"].decode_string() == memory->name) + if ((cell->type == "$memwr" || cell->type == "$memrd") && memory->name == cell->parameters["\\MEMID"].decode_string()) memcells.push_back(cell); } @@ -70,7 +70,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) for (auto cell : memcells) { - if (cell->type == "$memwr" && cell->parameters["\\MEMID"].decode_string() == memory->name) + if (cell->type == "$memwr" && memory->name == cell->parameters["\\MEMID"].decode_string()) { wr_ports++; del_cells.push_back(cell); @@ -97,7 +97,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) sig_wr_en.append(en); } - if (cell->type == "$memrd" && cell->parameters["\\MEMID"].decode_string() == memory->name) + if (cell->type == "$memrd" && memory->name == cell->parameters["\\MEMID"].decode_string()) { rd_ports++; del_cells.push_back(cell); @@ -129,7 +129,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) sstr << "$mem$" << memory->name << "$" << (autoidx++); RTLIL::Cell *mem = module->addCell(sstr.str(), "$mem"); - mem->parameters["\\MEMID"] = RTLIL::Const(memory->name); + mem->parameters["\\MEMID"] = RTLIL::Const(memory->name.str()); mem->parameters["\\WIDTH"] = RTLIL::Const(memory->width); mem->parameters["\\OFFSET"] = RTLIL::Const(memory->start_offset); mem->parameters["\\SIZE"] = RTLIL::Const(memory->size); diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index f1917b97..8dc66f2c 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -23,10 +23,10 @@ #include #include -static std::string genid(std::string name, std::string token1 = "", int i = -1, std::string token2 = "", int j = -1, std::string token3 = "", int k = -1, std::string token4 = "") +static std::string genid(RTLIL::IdString name, std::string token1 = "", int i = -1, std::string token2 = "", int j = -1, std::string token3 = "", int k = -1, std::string token4 = "") { std::stringstream sstr; - sstr << "$memory" << name << token1; + sstr << "$memory" << name.str() << token1; if (i >= 0) sstr << "[" << i << "]"; diff --git a/passes/memory/memory_unpack.cc b/passes/memory/memory_unpack.cc index 68e9a969..5a4c4eac 100644 --- a/passes/memory/memory_unpack.cc +++ b/passes/memory/memory_unpack.cc @@ -31,7 +31,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory) RTLIL::IdString mem_name = RTLIL::escape_id(memory->parameters.at("\\MEMID").decode_string()); while (module->memories.count(mem_name) != 0) - mem_name += stringf("_%d", autoidx++); + mem_name = mem_name.str() + stringf("_%d", autoidx++); RTLIL::Memory *mem = new RTLIL::Memory; mem->name = mem_name; @@ -47,7 +47,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory) for (int i = 0; i < num_rd_ports; i++) { RTLIL::Cell *cell = module->addCell(NEW_ID, "$memrd"); - cell->parameters["\\MEMID"] = mem_name; + cell->parameters["\\MEMID"] = mem_name.str(); cell->parameters["\\ABITS"] = memory->parameters.at("\\ABITS"); cell->parameters["\\WIDTH"] = memory->parameters.at("\\WIDTH"); cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_ENABLE")).extract(i, 1).as_const(); @@ -61,7 +61,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory) for (int i = 0; i < num_wr_ports; i++) { RTLIL::Cell *cell = module->addCell(NEW_ID, "$memwr"); - cell->parameters["\\MEMID"] = mem_name; + cell->parameters["\\MEMID"] = mem_name.str(); cell->parameters["\\ABITS"] = memory->parameters.at("\\ABITS"); cell->parameters["\\WIDTH"] = memory->parameters.at("\\WIDTH"); cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_ENABLE")).extract(i, 1).as_const(); diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 4182c6f5..c620531e 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -139,11 +139,12 @@ static bool compare_signals(RTLIL::SigBit &s1, RTLIL::SigBit &s2, SigPool ®s, static bool check_public_name(RTLIL::IdString id) { - if (id[0] == '$') + const std::string &id_str = id.str(); + if (id_str[0] == '$') return false; - if (id.substr(0, 2) == "\\_" && (id[id.size()-1] == '_' || id.find("_[") != std::string::npos)) + if (id_str.substr(0, 2) == "\\_" && (id_str[id_str.size()-1] == '_' || id_str.find("_[") != std::string::npos)) return false; - if (id.find(".$") != std::string::npos) + if (id_str.find(".$") != std::string::npos) return false; return true; } diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 5dab5eca..a13bb09c 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -183,7 +183,7 @@ static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool com log("\n"); } - cover_list("opt.opt_const.fine.group", "$not", "$pos", "$bu0", "$and", "$or", "$xor", "$xnor", cell->type); + cover_list("opt.opt_const.fine.group", "$not", "$pos", "$bu0", "$and", "$or", "$xor", "$xnor", cell->type.str()); module->remove(cell); OPT_DID_SOMETHING = true; @@ -288,7 +288,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo } if (new_a != RTLIL::State::Sm && RTLIL::SigSpec(new_a) != sig_a) { - cover_list("opt.opt_const.fine.A", "$logic_not", "$logic_and", "$logic_or", "$reduce_or", "$reduce_bool", cell->type); + cover_list("opt.opt_const.fine.A", "$logic_not", "$logic_and", "$logic_or", "$reduce_or", "$reduce_bool", cell->type.str()); log("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a)); cell->setPort("\\A", sig_a = new_a); @@ -315,7 +315,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo } if (new_b != RTLIL::State::Sm && RTLIL::SigSpec(new_b) != sig_b) { - cover_list("opt.opt_const.fine.B", "$logic_and", "$logic_or", cell->type); + cover_list("opt.opt_const.fine.B", "$logic_and", "$logic_or", cell->type.str()); log("Replacing port B of %s cell `%s' in module `%s' with constant driver: %s -> %s\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_b)); cell->setPort("\\B", sig_b = new_b); @@ -361,7 +361,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (0) { found_the_x_bit: cover_list("opt.opt_const.xbit", "$reduce_xor", "$reduce_xnor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", - "$lt", "$le", "$ge", "$gt", "$neg", "$add", "$sub", "$mul", "$div", "$mod", "$pow", cell->type); + "$lt", "$le", "$ge", "$gt", "$neg", "$add", "$sub", "$mul", "$div", "$mod", "$pow", cell->type.str()); if (cell->type == "$reduce_xor" || cell->type == "$reduce_xnor" || cell->type == "$lt" || cell->type == "$le" || cell->type == "$ge" || cell->type == "$gt") replace_cell(assign_map, module, cell, "x-bit in input", "\\Y", RTLIL::State::Sx); @@ -373,13 +373,13 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") && cell->getPort("\\Y").size() == 1 && invert_map.count(assign_map(cell->getPort("\\A"))) != 0) { - cover_list("opt.opt_const.invert.double", "$_INV_", "$not", "$logic_not", cell->type); + cover_list("opt.opt_const.invert.double", "$_INV_", "$not", "$logic_not", cell->type.str()); replace_cell(assign_map, module, cell, "double_invert", "\\Y", invert_map.at(assign_map(cell->getPort("\\A")))); goto next_cell; } if ((cell->type == "$_MUX_" || cell->type == "$mux") && invert_map.count(assign_map(cell->getPort("\\S"))) != 0) { - cover_list("opt.opt_const.invert.muxsel", "$_MUX_", "$mux", cell->type); + cover_list("opt.opt_const.invert.muxsel", "$_MUX_", "$mux", cell->type.str()); RTLIL::SigSpec tmp = cell->getPort("\\A"); cell->setPort("\\A", cell->getPort("\\B")); cell->setPort("\\B", tmp); @@ -497,7 +497,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo log_assert(SIZE(a) == SIZE(b)); for (int i = 0; i < SIZE(a); i++) { if (a[i].wire == NULL && b[i].wire == NULL && a[i] != b[i] && a[i].data <= RTLIL::State::S1 && b[i].data <= RTLIL::State::S1) { - cover_list("opt.opt_const.eqneq.isneq", "$eq", "$ne", "$eqx", "$nex", cell->type); + cover_list("opt.opt_const.eqneq.isneq", "$eq", "$ne", "$eqx", "$nex", cell->type.str()); RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ? RTLIL::State::S0 : RTLIL::State::S1); new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false); replace_cell(assign_map, module, cell, "isneq", "\\Y", new_y); @@ -510,7 +510,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo } if (new_a.size() == 0) { - cover_list("opt.opt_const.eqneq.empty", "$eq", "$ne", "$eqx", "$nex", cell->type); + cover_list("opt.opt_const.eqneq.empty", "$eq", "$ne", "$eqx", "$nex", cell->type.str()); RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ? RTLIL::State::S1 : RTLIL::State::S0); new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false); replace_cell(assign_map, module, cell, "empty", "\\Y", new_y); @@ -518,7 +518,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo } if (new_a.size() < a.size() || new_b.size() < b.size()) { - cover_list("opt.opt_const.eqneq.resize", "$eq", "$ne", "$eqx", "$nex", cell->type); + cover_list("opt.opt_const.eqneq.resize", "$eq", "$ne", "$eqx", "$nex", cell->type.str()); cell->setPort("\\A", new_a); cell->setPort("\\B", new_b); cell->parameters["\\A_WIDTH"] = new_a.size(); @@ -533,7 +533,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo RTLIL::SigSpec b = assign_map(cell->getPort("\\B")); if (a.is_fully_const()) { - cover_list("opt.opt_const.eqneq.swapconst", "$eq", "$ne", cell->type); + cover_list("opt.opt_const.eqneq.swapconst", "$eq", "$ne", cell->type.str()); RTLIL::SigSpec tmp = cell->getPort("\\A"); cell->setPort("\\A", cell->getPort("\\B")); cell->setPort("\\B", tmp); @@ -544,7 +544,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo RTLIL::SigSpec input = b; ACTION_DO("\\Y", cell->getPort("\\A")); } else { - cover_list("opt.opt_const.eqneq.isnot", "$eq", "$ne", cell->type); + cover_list("opt.opt_const.eqneq.isnot", "$eq", "$ne", cell->type.str()); cell->type = "$not"; cell->parameters.erase("\\B_WIDTH"); cell->parameters.erase("\\B_SIGNED"); @@ -603,9 +603,9 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (identity_wrt_a || identity_wrt_b) { if (identity_wrt_a) - cover_list("opt.opt_const.identwrt.a", "$add", "$sub", "$or", "$xor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", "$mul", "$div", cell->type); + cover_list("opt.opt_const.identwrt.a", "$add", "$sub", "$or", "$xor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", "$mul", "$div", cell->type.str()); if (identity_wrt_b) - cover_list("opt.opt_const.identwrt.b", "$add", "$sub", "$or", "$xor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", "$mul", "$div", cell->type); + cover_list("opt.opt_const.identwrt.b", "$add", "$sub", "$or", "$xor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", "$mul", "$div", cell->type.str()); log("Replacing %s cell `%s' in module `%s' with identity for port %c.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str(), identity_wrt_a ? 'A' : 'B'); @@ -630,14 +630,14 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->getPort("\\A") == RTLIL::SigSpec(0, 1) && cell->getPort("\\B") == RTLIL::SigSpec(1, 1)) { - cover_list("opt.opt_const.mux_bool", "$mux", "$_MUX_", cell->type); + cover_list("opt.opt_const.mux_bool", "$mux", "$_MUX_", cell->type.str()); replace_cell(assign_map, module, cell, "mux_bool", "\\Y", cell->getPort("\\S")); goto next_cell; } if (mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->getPort("\\A") == RTLIL::SigSpec(1, 1) && cell->getPort("\\B") == RTLIL::SigSpec(0, 1)) { - cover_list("opt.opt_const.mux_invert", "$mux", "$_MUX_", cell->type); + cover_list("opt.opt_const.mux_invert", "$mux", "$_MUX_", cell->type.str()); cell->setPort("\\A", cell->getPort("\\S")); cell->unsetPort("\\B"); cell->unsetPort("\\S"); @@ -655,7 +655,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo } if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->getPort("\\A") == RTLIL::SigSpec(0, 1)) { - cover_list("opt.opt_const.mux_and", "$mux", "$_MUX_", cell->type); + cover_list("opt.opt_const.mux_and", "$mux", "$_MUX_", cell->type.str()); cell->setPort("\\A", cell->getPort("\\S")); cell->unsetPort("\\S"); if (cell->type == "$mux") { @@ -674,7 +674,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo } if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->getPort("\\B") == RTLIL::SigSpec(1, 1)) { - cover_list("opt.opt_const.mux_or", "$mux", "$_MUX_", cell->type); + cover_list("opt.opt_const.mux_or", "$mux", "$_MUX_", cell->type.str()); cell->setPort("\\B", cell->getPort("\\S")); cell->unsetPort("\\S"); if (cell->type == "$mux") { @@ -697,7 +697,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo int width = cell->getPort("\\A").size(); if ((cell->getPort("\\A").is_fully_undef() && cell->getPort("\\B").is_fully_undef()) || cell->getPort("\\S").is_fully_undef()) { - cover_list("opt.opt_const.mux_undef", "$mux", "$pmux", cell->type); + cover_list("opt.opt_const.mux_undef", "$mux", "$pmux", cell->type.str()); replace_cell(assign_map, module, cell, "mux_undef", "\\Y", cell->getPort("\\A")); goto next_cell; } @@ -716,17 +716,17 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo new_s = new_s.extract(0, new_s.size()-1); } if (new_s.size() == 0) { - cover_list("opt.opt_const.mux_empty", "$mux", "$pmux", cell->type); + cover_list("opt.opt_const.mux_empty", "$mux", "$pmux", cell->type.str()); replace_cell(assign_map, module, cell, "mux_empty", "\\Y", new_a); goto next_cell; } if (new_a == RTLIL::SigSpec(RTLIL::State::S0) && new_b == RTLIL::SigSpec(RTLIL::State::S1)) { - cover_list("opt.opt_const.mux_sel01", "$mux", "$pmux", cell->type); + cover_list("opt.opt_const.mux_sel01", "$mux", "$pmux", cell->type.str()); replace_cell(assign_map, module, cell, "mux_sel01", "\\Y", new_s); goto next_cell; } if (cell->getPort("\\S").size() != new_s.size()) { - cover_list("opt.opt_const.mux_reduce", "$mux", "$pmux", cell->type); + cover_list("opt.opt_const.mux_reduce", "$mux", "$pmux", cell->type.str()); cell->setPort("\\A", new_a); cell->setPort("\\B", new_b); cell->setPort("\\S", new_s); diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index c1e33caf..bbf94d3b 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -178,7 +178,7 @@ struct OptRmdffPass : public Pass { dff_init_map.add(it.second, it.second->attributes.at("\\init")); mux_drivers.clear(); - std::vector dff_list; + std::vector dff_list; for (auto &it : mod_it.second->cells_) { if (it.second->type == "$mux" || it.second->type == "$pmux") { if (it.second->getPort("\\A").size() == it.second->getPort("\\B").size()) diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc index 3532b124..eb970329 100644 --- a/passes/opt/opt_share.cc +++ b/passes/opt/opt_share.cc @@ -60,10 +60,10 @@ struct OptShareWorker if (cell_hash_cache.count(cell) > 0) return cell_hash_cache[cell]; - std::string hash_string = cell->type + "\n"; + std::string hash_string = cell->type.str() + "\n"; for (auto &it : cell->parameters) - hash_string += "P " + it.first + "=" + it.second.as_string() + "\n"; + hash_string += "P " + it.first.str() + "=" + it.second.as_string() + "\n"; const std::map *conn = &cell->connections(); std::map alt_conn; @@ -95,10 +95,10 @@ struct OptShareWorker continue; RTLIL::SigSpec sig = it.second; assign_map.apply(sig); - hash_string += "C " + it.first + "="; + hash_string += "C " + it.first.str() + "="; for (auto &chunk : sig.chunks()) { if (chunk.wire) - hash_string += "{" + chunk.wire->name + " " + + hash_string += "{" + chunk.wire->name.str() + " " + int_to_hash_string(chunk.offset) + " " + int_to_hash_string(chunk.width) + "}"; else diff --git a/passes/proc/proc_clean.cc b/passes/proc/proc_clean.cc index e4c52663..13be0ddb 100644 --- a/passes/proc/proc_clean.cc +++ b/passes/proc/proc_clean.cc @@ -150,7 +150,7 @@ struct ProcCleanPass : public Pass { extra_args(args, 1, design); for (auto mod : design->modules()) { - std::vector delme; + std::vector delme; if (!design->selected(mod)) continue; for (auto &proc_it : mod->processes) { diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index 8a2dd929..f07ad943 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -471,7 +471,7 @@ struct EvalPass : public Pass { if (shows.size() == 0) { for (auto &it : module->wires_) if (it.second->port_output) - shows.push_back(it.second->name); + shows.push_back(it.second->name.str()); } if (tables.empty()) diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index 25b9e1d1..affd685e 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -27,7 +27,7 @@ struct dff_map_info_t { RTLIL::SigSpec sig_d, sig_clk, sig_arst; bool clk_polarity, arst_polarity; RTLIL::Const arst_value; - std::vector cells; + std::vector cells; }; struct dff_map_bit_info_t { @@ -37,7 +37,7 @@ struct dff_map_bit_info_t { RTLIL::Cell *cell; }; -static bool consider_wire(RTLIL::Wire *wire, std::map &dff_dq_map) +static bool consider_wire(RTLIL::Wire *wire, std::map &dff_dq_map) { if (wire->name[0] == '$' || dff_dq_map.count(wire->name)) return false; @@ -46,7 +46,7 @@ static bool consider_wire(RTLIL::Wire *wire, std::map &dff_cells, RTLIL::Cell *cell) +static bool consider_cell(RTLIL::Design *design, std::set &dff_cells, RTLIL::Cell *cell) { if (cell->name[0] == '$' || dff_cells.count(cell->name)) return false; @@ -73,7 +73,7 @@ static bool compare_cells(RTLIL::Cell *cell1, RTLIL::Cell *cell2) return true; } -static void find_dff_wires(std::set &dff_wires, RTLIL::Module *module) +static void find_dff_wires(std::set &dff_wires, RTLIL::Module *module) { CellTypes ct; ct.setup_internals_mem(); @@ -93,7 +93,7 @@ static void find_dff_wires(std::set &dff_wires, RTLIL::Module *modu } } -static void create_dff_dq_map(std::map &map, RTLIL::Design *design, RTLIL::Module *module) +static void create_dff_dq_map(std::map &map, RTLIL::Design *design, RTLIL::Module *module) { std::map bit_info; SigMap sigmap(module); @@ -160,7 +160,7 @@ static void create_dff_dq_map(std::map &map, RTLIL: } } - std::map empty_dq_map; + std::map empty_dq_map; for (auto &it : module->wires_) { if (!consider_wire(it.second, empty_dq_map)) @@ -208,7 +208,7 @@ static void create_dff_dq_map(std::map &map, RTLIL: } } -static RTLIL::Wire *add_new_wire(RTLIL::Module *module, std::string name, int width = 1) +static RTLIL::Wire *add_new_wire(RTLIL::Module *module, RTLIL::IdString name, int width = 1) { if (module->count_id(name)) log_error("Attempting to create wire %s, but a wire of this name exists already! Hint: Try another value for -sep.\n", log_id(name)); @@ -294,13 +294,13 @@ struct ExposePass : public Pass { CellTypes ct(design); - std::map> dff_dq_maps; - std::map> dff_cells; + std::map> dff_dq_maps; + std::map> dff_cells; if (flag_evert_dff) { RTLIL::Module *first_module = NULL; - std::set shared_dff_wires; + std::set shared_dff_wires; for (auto &mod_it : design->modules_) { @@ -317,7 +317,7 @@ struct ExposePass : public Pass { shared_dff_wires.insert(it.first); first_module = mod_it.second; } else { - std::set new_shared_dff_wires; + std::set new_shared_dff_wires; for (auto &it : shared_dff_wires) { if (!dff_dq_maps[mod_it.second].count(it)) continue; @@ -332,7 +332,7 @@ struct ExposePass : public Pass { if (flag_shared) for (auto &map_it : dff_dq_maps) { - std::map new_map; + std::map new_map; for (auto &it : map_it.second) if (shared_dff_wires.count(it.first)) new_map[it.first] = it.second; @@ -345,8 +345,8 @@ struct ExposePass : public Pass { dff_cells[it1.first].insert(it3); } - std::set shared_wires, shared_cells; - std::set used_names; + std::set shared_wires, shared_cells; + std::set used_names; if (flag_shared) { @@ -359,7 +359,7 @@ struct ExposePass : public Pass { if (!design->selected(module)) continue; - std::set dff_wires; + std::set dff_wires; if (flag_dff) find_dff_wires(dff_wires, module); @@ -379,7 +379,7 @@ struct ExposePass : public Pass { } else { - std::vector delete_shared_wires, delete_shared_cells; + std::vector delete_shared_wires, delete_shared_cells; for (auto &it : shared_wires) { @@ -441,7 +441,7 @@ struct ExposePass : public Pass { if (!design->selected(module)) continue; - std::set dff_wires; + std::set dff_wires; if (flag_dff && !flag_shared) find_dff_wires(dff_wires, module); @@ -467,7 +467,7 @@ struct ExposePass : public Pass { } if (flag_cut) { - RTLIL::Wire *in_wire = add_new_wire(module, it.second->name + sep + "i", it.second->width); + RTLIL::Wire *in_wire = add_new_wire(module, it.second->name.str() + sep + "i", it.second->width); in_wire->port_input = true; out_to_in_map.add(sigmap(it.second), in_wire); } @@ -511,7 +511,7 @@ struct ExposePass : public Pass { cell->setPort("\\Q", cell_q_bits); } - RTLIL::Wire *wire_q = add_new_wire(module, wire->name + sep + "q", wire->width); + RTLIL::Wire *wire_q = add_new_wire(module, wire->name.str() + sep + "q", wire->width); wire_q->port_input = true; log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_q->name)); @@ -525,12 +525,12 @@ struct ExposePass : public Pass { } module->connect(connect_q); - RTLIL::Wire *wire_d = add_new_wire(module, wire->name + sep + "d", wire->width); + RTLIL::Wire *wire_d = add_new_wire(module, wire->name.str() + sep + "d", wire->width); wire_d->port_output = true; log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_d->name)); module->connect(RTLIL::SigSig(wire_d, info.sig_d)); - RTLIL::Wire *wire_c = add_new_wire(module, wire->name + sep + "c"); + RTLIL::Wire *wire_c = add_new_wire(module, wire->name.str() + sep + "c"); wire_c->port_output = true; log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_c->name)); if (info.clk_polarity) { @@ -546,7 +546,7 @@ struct ExposePass : public Pass { if (info.sig_arst != RTLIL::State::Sm) { - RTLIL::Wire *wire_r = add_new_wire(module, wire->name + sep + "r"); + RTLIL::Wire *wire_r = add_new_wire(module, wire->name.str() + sep + "r"); wire_r->port_output = true; log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_r->name)); if (info.arst_polarity) { @@ -560,7 +560,7 @@ struct ExposePass : public Pass { c->setPort("\\Y", wire_r); } - RTLIL::Wire *wire_v = add_new_wire(module, wire->name + sep + "v", wire->width); + RTLIL::Wire *wire_v = add_new_wire(module, wire->name.str() + sep + "v", wire->width); wire_v->port_output = true; log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_v->name)); module->connect(RTLIL::SigSig(wire_v, info.arst_value)); @@ -593,7 +593,7 @@ struct ExposePass : public Pass { if (!p->port_input && !p->port_output) continue; - RTLIL::Wire *w = add_new_wire(module, cell->name + sep + RTLIL::unescape_id(p->name), p->width); + RTLIL::Wire *w = add_new_wire(module, cell->name.str() + sep + RTLIL::unescape_id(p->name), p->width); if (p->port_input) w->port_output = true; if (p->port_output) @@ -615,7 +615,7 @@ struct ExposePass : public Pass { { for (auto &it : cell->connections()) { - RTLIL::Wire *w = add_new_wire(module, cell->name + sep + RTLIL::unescape_id(it.first), it.second.size()); + RTLIL::Wire *w = add_new_wire(module, cell->name.str() + sep + RTLIL::unescape_id(it.first), it.second.size()); if (ct.cell_input(cell->type, it.first)) w->port_output = true; if (ct.cell_output(cell->type, it.first)) diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 430628e4..fd3d405a 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -1160,19 +1160,19 @@ struct SatPass : public Pass { if (set_def_inputs) { for (auto &it : module->wires_) if (it.second->port_input) - sets_def.push_back(it.second->name); + sets_def.push_back(it.second->name.str()); } if (show_inputs) { for (auto &it : module->wires_) if (it.second->port_input) - shows.push_back(it.second->name); + shows.push_back(it.second->name.str()); } if (show_outputs) { for (auto &it : module->wires_) if (it.second->port_output) - shows.push_back(it.second->name); + shows.push_back(it.second->name.str()); } if (tempinduct) diff --git a/passes/sat/share.cc b/passes/sat/share.cc index ea7a9f63..4484d677 100644 --- a/passes/sat/share.cc +++ b/passes/sat/share.cc @@ -29,13 +29,13 @@ struct ShareWorkerConfig bool opt_force; bool opt_aggressive; bool opt_fast; - std::set generic_uni_ops, generic_bin_ops, generic_cbin_ops; + std::set generic_uni_ops, generic_bin_ops, generic_cbin_ops; }; struct ShareWorker { ShareWorkerConfig config; - std::set generic_ops; + std::set generic_ops; RTLIL::Design *design; RTLIL::Module *module; diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index 7712d18b..16518b7d 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -29,7 +29,7 @@ struct cell_mapping { std::string cell_name; std::map ports; }; -static std::map cell_mappings; +static std::map cell_mappings; static void logmap(std::string dff) { @@ -319,7 +319,7 @@ static bool expand_cellmap(std::string pattern, std::string inv) bool return_status = false; for (auto &it : cell_mappings) { - std::string from = it.first, to = it.first; + std::string from = it.first.str(), to = it.first.str(); if (from.size() != pattern.size()) continue; for (size_t i = 0; i < from.size(); i++) { diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index 53bc00da..6ebac265 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -34,7 +34,7 @@ namespace { public: bool ignore_parameters; - std::set> ignored_parameters; + std::set> ignored_parameters; std::set cell_attr, wire_attr; SubCircuitSolver() : ignore_parameters(false) @@ -106,10 +106,10 @@ namespace if (!ignore_parameters) { std::map needle_param, haystack_param; for (auto &it : needleCell->parameters) - if (!ignored_parameters.count(std::pair(needleCell->type, it.first))) + if (!ignored_parameters.count(std::pair(needleCell->type, it.first))) needle_param[it.first] = unified_param(needleCell->type, it.first, it.second); for (auto &it : haystackCell->parameters) - if (!ignored_parameters.count(std::pair(haystackCell->type, it.first))) + if (!ignored_parameters.count(std::pair(haystackCell->type, it.first))) haystack_param[it.first] = unified_param(haystackCell->type, it.first, it.second); if (needle_param != haystack_param) return false; @@ -127,7 +127,7 @@ namespace for (auto &conn : needleCell->connections()) { RTLIL::SigSpec needleSig = conn.second; - RTLIL::SigSpec haystackSig = haystackCell->getPort(portMapping.at(conn.first)); + RTLIL::SigSpec haystackSig = haystackCell->getPort(portMapping.at(conn.first.str())); for (int i = 0; i < std::min(needleSig.size(), haystackSig.size()); i++) { RTLIL::Wire *needleWire = needleSig[i].wire, *haystackWire = haystackSig[i].wire; @@ -201,14 +201,14 @@ namespace if (sel && !sel->selected(mod, cell)) continue; - std::string type = cell->type; + std::string type = cell->type.str(); if (sel == NULL && type.substr(0, 2) == "\\$") type = type.substr(1); - graph.createNode(cell->name, type, (void*)cell); + graph.createNode(cell->name.str(), type, (void*)cell); for (auto &conn : cell->connections()) { - graph.createPort(cell->name, conn.first, conn.second.size()); + graph.createPort(cell->name.str(), conn.first.str(), conn.second.size()); if (split && split->count(std::pair(cell->type, conn.first)) > 0) continue; @@ -226,9 +226,9 @@ namespace if (bit == RTLIL::State::S0) node = "$const$0"; if (bit == RTLIL::State::S1) node = "$const$1"; if (bit == RTLIL::State::Sz) node = "$const$z"; - graph.createConnection(cell->name, conn.first, i, node, "\\Y", 0); + graph.createConnection(cell->name.str(), conn.first.str(), i, node, "\\Y", 0); } else - graph.createConstant(cell->name, conn.first, i, int(bit.data)); + graph.createConstant(cell->name.str(), conn.first.str(), i, int(bit.data)); continue; } @@ -246,7 +246,7 @@ namespace } bit_ref_t &bit_ref = sig_bit_ref[bit]; - graph.createConnection(bit_ref.cell, bit_ref.port, bit_ref.bit, cell->name, conn.first, i); + graph.createConnection(bit_ref.cell, bit_ref.port, bit_ref.bit, cell->name.str(), conn.first.str(), i); } } } @@ -293,7 +293,7 @@ namespace RTLIL::Cell *replace(RTLIL::Module *needle, RTLIL::Module *haystack, SubCircuit::Solver::Result &match) { SigMap sigmap(needle); - SigSet> sig2port; + SigSet> sig2port; // create new cell RTLIL::Cell *cell = haystack->addCell(stringf("$extract$%s$%d", needle->name.c_str(), autoidx++), needle->name); @@ -303,7 +303,7 @@ namespace RTLIL::Wire *wire = it.second; if (wire->port_id > 0) { for (int i = 0; i < wire->width; i++) - sig2port.insert(sigmap(RTLIL::SigSpec(wire, i)), std::pair(wire->name, i)); + sig2port.insert(sigmap(RTLIL::SigSpec(wire, i)), std::pair(wire->name, i)); cell->setPort(wire->name, RTLIL::SigSpec(RTLIL::State::Sz, wire->width)); } } @@ -320,10 +320,10 @@ namespace for (auto &conn : needle_cell->connections()) { RTLIL::SigSpec sig = sigmap(conn.second); - if (mapping.portMapping.count(conn.first) > 0 && sig2port.has(sigmap(sig))) { + if (mapping.portMapping.count(conn.first.str()) > 0 && sig2port.has(sigmap(sig))) { for (int i = 0; i < sig.size(); i++) for (auto &port : sig2port.find(sig[i])) { - RTLIL::SigSpec bitsig = haystack_cell->getPort(mapping.portMapping[conn.first]).extract(i, 1); + RTLIL::SigSpec bitsig = haystack_cell->getPort(mapping.portMapping[conn.first.str()]).extract(i, 1); RTLIL::SigSpec new_sig = cell->getPort(port.first); new_sig.replace(port.second, bitsig); cell->setPort(port.first, new_sig); @@ -561,7 +561,7 @@ struct ExtractPass : public Pass { continue; } if (args[argidx] == "-ignore_param" && argidx+2 < args.size()) { - solver.ignored_parameters.insert(std::pair(RTLIL::escape_id(args[argidx+1]), RTLIL::escape_id(args[argidx+2]))); + solver.ignored_parameters.insert(std::pair(RTLIL::escape_id(args[argidx+1]), RTLIL::escape_id(args[argidx+2]))); argidx += 2; continue; } diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index f1f334f6..960578b0 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -24,7 +24,7 @@ #include #include -extern void simplemap_get_mappers(std::map &mappers); +extern void simplemap_get_mappers(std::map &mappers); static void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell) { @@ -382,7 +382,7 @@ static void simplemap_dlatch(RTLIL::Module *module, RTLIL::Cell *cell) } } -void simplemap_get_mappers(std::map &mappers) +void simplemap_get_mappers(std::map &mappers) { mappers["$not"] = simplemap_not; mappers["$pos"] = simplemap_pos; @@ -431,7 +431,7 @@ struct SimplemapPass : public Pass { log_header("Executing SIMPLEMAP pass (map simple cells to gate primitives).\n"); extra_args(args, 1, design); - std::map mappers; + std::map mappers; simplemap_get_mappers(mappers); for (auto mod : design->modules()) { diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 1f812e52..2bcd3003 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -29,7 +29,7 @@ #include "passes/techmap/techmap.inc" // see simplemap.cc -extern void simplemap_get_mappers(std::map &mappers); +extern void simplemap_get_mappers(std::map &mappers); static void apply_prefix(std::string prefix, std::string &id) { @@ -44,7 +44,7 @@ static void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module std::vector chunks = sig; for (auto &chunk : chunks) if (chunk.wire != NULL) { - std::string wire_name = chunk.wire->name; + std::string wire_name = chunk.wire->name.str(); apply_prefix(prefix, wire_name); log_assert(module->wires_.count(wire_name) > 0); chunk.wire = module->wires_[wire_name]; @@ -54,7 +54,7 @@ static void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module struct TechmapWorker { - std::map simplemap_mappers; + std::map simplemap_mappers; std::map>, RTLIL::Module*> techmap_cache; std::map techmap_do_cache; std::set module_queue; @@ -80,7 +80,7 @@ struct TechmapWorker std::string constmap_tpl_name(SigMap &sigmap, RTLIL::Module *tpl, RTLIL::Cell *cell, bool verbose) { std::string constmap_info; - std::map> connbits_map; + std::map> connbits_map; for (auto conn : cell->connections()) for (int i = 0; i < SIZE(conn.second); i++) { @@ -96,7 +96,7 @@ struct TechmapWorker constmap_info += stringf("|%s %d %s %d", log_id(conn.first), i, log_id(connbits_map.at(bit).first), connbits_map.at(bit).second); } else - connbits_map[bit] = std::pair(conn.first, i);stringf("%s %d", log_id(conn.first), i, bit.data); + connbits_map[bit] = std::pair(conn.first, i);stringf("%s %d", log_id(conn.first), i, bit.data); } return stringf("$paramod$constmap:%s%s", sha1(constmap_info).c_str(), tpl->name.c_str()); @@ -156,7 +156,7 @@ struct TechmapWorker for (auto &it : tpl->cells_) if (it.first == "\\_TECHMAP_REPLACE_") { orig_cell_name = cell->name; - module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name); + module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str()); break; } @@ -165,8 +165,8 @@ struct TechmapWorker for (auto &it : tpl->wires_) { if (it.second->port_id > 0) positional_ports[stringf("$%d", it.second->port_id)] = it.first; - std::string w_name = it.second->name; - apply_prefix(cell->name, w_name); + std::string w_name = it.second->name.str(); + apply_prefix(cell->name.str(), w_name); RTLIL::Wire *w = module->addWire(w_name, it.second); w->port_input = false; w->port_output = false; @@ -192,11 +192,11 @@ struct TechmapWorker if (w->port_output) { c.first = it.second; c.second = RTLIL::SigSpec(w); - apply_prefix(cell->name, c.second, module); + apply_prefix(cell->name.str(), c.second, module); } else { c.first = RTLIL::SigSpec(w); c.second = it.second; - apply_prefix(cell->name, c.first, module); + apply_prefix(cell->name.str(), c.first, module); } if (c.second.size() > c.first.size()) c.second.remove(c.first.size(), c.second.size() - c.first.size()); @@ -219,12 +219,12 @@ struct TechmapWorker for (auto &it : tpl->cells_) { - RTLIL::IdString c_name = it.second->name; + std::string c_name = it.second->name.str(); if (!flatten_mode && c_name == "\\_TECHMAP_REPLACE_") c_name = orig_cell_name; else - apply_prefix(cell->name, c_name); + apply_prefix(cell->name.str(), c_name); RTLIL::Cell *c = module->addCell(c_name, it.second); design->select(module, c); @@ -233,15 +233,15 @@ struct TechmapWorker c->type = c->type.substr(1); for (auto &it2 : c->connections_) { - apply_prefix(cell->name, it2.second, module); + apply_prefix(cell->name.str(), it2.second, module); port_signal_map.apply(it2.second); } } for (auto &it : tpl->connections()) { RTLIL::SigSig c = it; - apply_prefix(cell->name, c.first, module); - apply_prefix(cell->name, c.second, module); + apply_prefix(cell->name.str(), c.first, module); + apply_prefix(cell->name.str(), c.second, module); port_signal_map.apply(c.first); port_signal_map.apply(c.second); module->connect(c); @@ -271,7 +271,7 @@ struct TechmapWorker continue; if (celltypeMap.count(cell->type) == 0) { - if (assert_mode && cell->type.back() != '_') + if (assert_mode && cell->type.str().back() != '_') log_error("(ASSERT MODE) No matching template cell for type %s found.\n", log_id(cell->type)); continue; } @@ -313,7 +313,7 @@ struct TechmapWorker for (auto &tpl_name : celltypeMap.at(cell->type)) { - std::string derived_name = tpl_name; + RTLIL::IdString derived_name = tpl_name; RTLIL::Module *tpl = map->modules_[tpl_name]; std::map parameters = cell->parameters; @@ -499,7 +499,7 @@ struct TechmapWorker if (!wire->port_input || wire->port_output) continue; - std::string port_name = wire->name; + RTLIL::IdString port_name = wire->name; tpl->rename(wire, NEW_ID); RTLIL::Wire *new_wire = tpl->addWire(port_name, wire); diff --git a/passes/tests/test_autotb.cc b/passes/tests/test_autotb.cc index 844bcbc9..d2600227 100644 --- a/passes/tests/test_autotb.cc +++ b/passes/tests/test_autotb.cc @@ -109,8 +109,8 @@ static void autotest(FILE *f, RTLIL::Design *design, int num_iter) RTLIL::Wire *wire = it2->second; if (wire->port_output) { count_ports++; - signal_out[idy("sig", mod->name, wire->name)] = wire->width; - fprintf(f, "wire [%d:0] %s;\n", wire->width-1, idy("sig", mod->name, wire->name).c_str()); + signal_out[idy("sig", mod->name.str(), wire->name.str())] = wire->width; + fprintf(f, "wire [%d:0] %s;\n", wire->width-1, idy("sig", mod->name.str(), wire->name.str()).c_str()); } else if (wire->port_input) { count_ports++; bool is_clksignal = wire->get_bool_attribute("\\gentb_clock"); @@ -124,25 +124,25 @@ static void autotest(FILE *f, RTLIL::Design *design, int num_iter) is_clksignal = true; } if (is_clksignal && wire->attributes.count("\\gentb_constant") == 0) { - signal_clk[idy("sig", mod->name, wire->name)] = wire->width; + signal_clk[idy("sig", mod->name.str(), wire->name.str())] = wire->width; } else { - signal_in[idy("sig", mod->name, wire->name)] = wire->width; + signal_in[idy("sig", mod->name.str(), wire->name.str())] = wire->width; if (wire->attributes.count("\\gentb_constant") != 0) - signal_const[idy("sig", mod->name, wire->name)] = wire->attributes["\\gentb_constant"].as_string(); + signal_const[idy("sig", mod->name.str(), wire->name.str())] = wire->attributes["\\gentb_constant"].as_string(); } - fprintf(f, "reg [%d:0] %s;\n", wire->width-1, idy("sig", mod->name, wire->name).c_str()); + fprintf(f, "reg [%d:0] %s;\n", wire->width-1, idy("sig", mod->name.str(), wire->name.str()).c_str()); } } - fprintf(f, "%s %s(\n", id(mod->name).c_str(), idy("uut", mod->name).c_str()); + fprintf(f, "%s %s(\n", id(mod->name.str()).c_str(), idy("uut", mod->name.str()).c_str()); for (auto it2 = mod->wires_.begin(); it2 != mod->wires_.end(); it2++) { RTLIL::Wire *wire = it2->second; if (wire->port_output || wire->port_input) - fprintf(f, "\t.%s(%s)%s\n", id(wire->name).c_str(), - idy("sig", mod->name, wire->name).c_str(), --count_ports ? "," : ""); + fprintf(f, "\t.%s(%s)%s\n", id(wire->name.str()).c_str(), + idy("sig", mod->name.str(), wire->name.str()).c_str(), --count_ports ? "," : ""); } fprintf(f, ");\n\n"); - fprintf(f, "task %s;\n", idy(mod->name, "reset").c_str()); + fprintf(f, "task %s;\n", idy(mod->name.str(), "reset").c_str()); fprintf(f, "begin\n"); int delay_counter = 0; for (auto it = signal_in.begin(); it != signal_in.end(); it++) @@ -169,7 +169,7 @@ static void autotest(FILE *f, RTLIL::Design *design, int num_iter) fprintf(f, "end\n"); fprintf(f, "endtask\n\n"); - fprintf(f, "task %s;\n", idy(mod->name, "update_data").c_str()); + fprintf(f, "task %s;\n", idy(mod->name.str(), "update_data").c_str()); fprintf(f, "begin\n"); delay_counter = 0; for (auto it = signal_in.begin(); it != signal_in.end(); it++) { @@ -181,7 +181,7 @@ static void autotest(FILE *f, RTLIL::Design *design, int num_iter) fprintf(f, "end\n"); fprintf(f, "endtask\n\n"); - fprintf(f, "task %s;\n", idy(mod->name, "update_clock").c_str()); + fprintf(f, "task %s;\n", idy(mod->name.str(), "update_clock").c_str()); fprintf(f, "begin\n"); if (signal_clk.size()) { fprintf(f, "\txorshift128;\n"); @@ -203,7 +203,7 @@ static void autotest(FILE *f, RTLIL::Design *design, int num_iter) std::vector header1; std::string header2 = ""; - fprintf(f, "task %s;\n", idy(mod->name, "print_status").c_str()); + fprintf(f, "task %s;\n", idy(mod->name.str(), "print_status").c_str()); fprintf(f, "begin\n"); fprintf(f, "\t$display(\"#OUT# %%b %%b %%b %%t %%d\", {"); if (signal_in.size()) @@ -265,7 +265,7 @@ static void autotest(FILE *f, RTLIL::Design *design, int num_iter) fprintf(f, "end\n"); fprintf(f, "endtask\n\n"); - fprintf(f, "task %s;\n", idy(mod->name, "print_header").c_str()); + fprintf(f, "task %s;\n", idy(mod->name.str(), "print_header").c_str()); fprintf(f, "begin\n"); fprintf(f, "\t$display(\"#OUT#\");\n"); for (auto &hdr : header1) @@ -275,15 +275,15 @@ static void autotest(FILE *f, RTLIL::Design *design, int num_iter) fprintf(f, "end\n"); fprintf(f, "endtask\n\n"); - fprintf(f, "task %s;\n", idy(mod->name, "test").c_str()); + fprintf(f, "task %s;\n", idy(mod->name.str(), "test").c_str()); fprintf(f, "begin\n"); - fprintf(f, "\t$display(\"#OUT#\\n#OUT# ==== %s ====\");\n", idy(mod->name).c_str()); - fprintf(f, "\t%s;\n", idy(mod->name, "reset").c_str()); + fprintf(f, "\t$display(\"#OUT#\\n#OUT# ==== %s ====\");\n", idy(mod->name.str()).c_str()); + fprintf(f, "\t%s;\n", idy(mod->name.str(), "reset").c_str()); fprintf(f, "\tfor (i=0; i<%d; i=i+1) begin\n", num_iter); - fprintf(f, "\t\tif (i %% 20 == 0) %s;\n", idy(mod->name, "print_header").c_str()); - fprintf(f, "\t\t#100; %s;\n", idy(mod->name, "update_data").c_str()); - fprintf(f, "\t\t#100; %s;\n", idy(mod->name, "update_clock").c_str()); - fprintf(f, "\t\t#100; %s;\n", idy(mod->name, "print_status").c_str()); + fprintf(f, "\t\tif (i %% 20 == 0) %s;\n", idy(mod->name.str(), "print_header").c_str()); + fprintf(f, "\t\t#100; %s;\n", idy(mod->name.str(), "update_data").c_str()); + fprintf(f, "\t\t#100; %s;\n", idy(mod->name.str(), "update_clock").c_str()); + fprintf(f, "\t\t#100; %s;\n", idy(mod->name.str(), "print_status").c_str()); fprintf(f, "\tend\n"); fprintf(f, "end\n"); fprintf(f, "endtask\n\n"); @@ -294,7 +294,7 @@ static void autotest(FILE *f, RTLIL::Design *design, int num_iter) fprintf(f, "\t// $dumpvars(0, testbench);\n"); for (auto it = design->modules_.begin(); it != design->modules_.end(); it++) if (!it->second->get_bool_attribute("\\gentb_skip")) - fprintf(f, "\t%s;\n", idy(it->first, "test").c_str()); + fprintf(f, "\t%s;\n", idy(it->first.str(), "test").c_str()); fprintf(f, "\t$finish;\n"); fprintf(f, "end\n\n"); -- cgit v1.2.3