From c094c53de83707a5bf1b268640283f1dde235873 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 23 Jul 2014 20:32:28 +0200 Subject: Removed RTLIL::SigSpec::optimize() --- passes/abc/blifparse.cc | 3 --- passes/cmds/setundef.cc | 1 - passes/cmds/show.cc | 3 --- passes/cmds/splice.cc | 2 -- passes/cmds/splitnets.cc | 2 +- passes/fsm/fsm_map.cc | 5 ----- passes/memory/memory_collect.cc | 7 ------- passes/memory/memory_dff.cc | 1 - passes/memory/memory_share.cc | 2 -- passes/opt/opt_clean.cc | 2 -- passes/opt/opt_const.cc | 2 -- passes/proc/proc_dff.cc | 4 ---- passes/proc/proc_init.cc | 2 -- passes/sat/eval.cc | 3 --- passes/sat/freduce.cc | 10 +++++----- passes/sat/sat.cc | 5 ----- 16 files changed, 6 insertions(+), 48 deletions(-) (limited to 'passes') diff --git a/passes/abc/blifparse.cc b/passes/abc/blifparse.cc index 47fa0f82..04977b36 100644 --- a/passes/abc/blifparse.cc +++ b/passes/abc/blifparse.cc @@ -212,9 +212,6 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name) goto continue_without_read; } - input_sig.optimize(); - output_sig.optimize(); - RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = "$lut"; diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 63d5bb9a..6c4bb16c 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -144,7 +144,6 @@ struct SetundefPass : public Pass { RTLIL::SigSpec bits; for (int i = 0; i < c.width; i++) bits.append(worker.next_bit()); - bits.optimize(); module->connections.push_back(RTLIL::SigSig(c, bits)); } } diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index 37fe4404..6b37b7bb 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -171,8 +171,6 @@ struct ShowWorker std::string gen_signode_simple(RTLIL::SigSpec sig, bool range_check = true) { - sig.optimize(); - if (sig.chunks().size() == 0) { fprintf(f, "v%d [ label=\"\" ];\n", single_idx_count); return stringf("v%d", single_idx_count++); @@ -199,7 +197,6 @@ struct ShowWorker if (net.empty()) { std::string label_string; - sig.optimize(); int pos = sig.size()-1; int idx = single_idx_count++; for (int i = int(sig.chunks().size())-1; i >= 0; i--) { diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc index aed9c076..68e8951f 100644 --- a/passes/cmds/splice.cc +++ b/passes/cmds/splice.cc @@ -82,7 +82,6 @@ struct SpliceWorker module->add(cell); } - new_sig.optimize(); sliced_signals_cache[sig] = new_sig; return new_sig; @@ -143,7 +142,6 @@ struct SpliceWorker module->add(cell); } - new_sig.optimize(); spliced_signals_cache[sig] = new_sig; log(" Created spliced signal: %s -> %s\n", log_signal(sig), log_signal(new_sig)); diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc index c40ff2c4..c65b6a5f 100644 --- a/passes/cmds/splitnets.cc +++ b/passes/cmds/splitnets.cc @@ -141,7 +141,7 @@ struct SplitnetsPass : public Pass { if (!ct.cell_output(c.second->type, p.first)) continue; - RTLIL::SigSpec sig = p.second.optimized(); + RTLIL::SigSpec sig = p.second; for (auto &chunk : sig.chunks()) { if (chunk.wire == NULL) continue; diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index 9dda2ba8..cee26762 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -42,13 +42,10 @@ static void implement_pattern_cache(RTLIL::Module *module, std::mapparameters["\\SIZE"] = RTLIL::Const(memory->size); mem->parameters["\\ABITS"] = RTLIL::Const(addr_bits); - sig_wr_clk_enable.optimize(); - sig_wr_clk_polarity.optimize(); - assert(sig_wr_clk.size() == wr_ports); assert(sig_wr_clk_enable.size() == wr_ports && sig_wr_clk_enable.is_fully_const()); assert(sig_wr_clk_polarity.size() == wr_ports && sig_wr_clk_polarity.is_fully_const()); @@ -158,10 +155,6 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) mem->connections["\\WR_DATA"] = sig_wr_data; mem->connections["\\WR_EN"] = sig_wr_en; - sig_rd_clk_enable.optimize(); - sig_rd_clk_polarity.optimize(); - sig_rd_transparent.optimize(); - assert(sig_rd_clk.size() == rd_ports); assert(sig_rd_clk_enable.size() == rd_ports && sig_rd_clk_enable.is_fully_const()); assert(sig_rd_clk_polarity.size() == rd_ports && sig_rd_clk_polarity.is_fully_const()); diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index b1f1e22b..56915776 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -69,7 +69,6 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI replaced_this_bit:; } - sig.optimize(); return true; } diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index 38eff996..dd2a32ca 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -439,8 +439,6 @@ struct MemoryShareWorker merged_en.replace(k, cell_en.extract(k, 1)); merged_data.replace(k, cell_data.extract(k, 1)); } - merged_en.optimize(); - merged_data.optimize(); } // Connect the new EN and DATA signals and remove the old write port. diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 0be36606..ba0aadc6 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -241,8 +241,6 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool new_conn.second.append_bit(s2[i]); } if (new_conn.first.size() > 0) { - new_conn.first.optimize(); - new_conn.second.optimize(); used_signals.add(new_conn.first); used_signals.add(new_conn.second); module->connections.push_back(new_conn); diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index ff139854..800fbf10 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -481,8 +481,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo } if (new_a.size() < a.size() || new_b.size() < b.size()) { - new_a.optimize(); - new_b.optimize(); cell->connections["\\A"] = new_a; cell->connections["\\B"] = new_b; cell->parameters["\\A_WIDTH"] = new_a.size(); diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index 8e5fbe8f..a8aba903 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -352,10 +352,6 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) ce.assign_map.apply(rstval); ce.assign_map.apply(sig); - insig.optimize(); - rstval.optimize(); - sig.optimize(); - if (rstval == sig) { rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size()); sync_level = NULL; diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc index ba1fb5ab..4c9b6bcd 100644 --- a/passes/proc/proc_init.cc +++ b/passes/proc/proc_init.cc @@ -28,7 +28,6 @@ static void proc_get_const(RTLIL::SigSpec &sig, RTLIL::CaseRule &rule) assert(rule.compare.size() == 0); while (1) { - sig.optimize(); RTLIL::SigSpec tmp = sig; for (auto &it : rule.actions) tmp.replace(it.first, it.second); @@ -53,7 +52,6 @@ static void proc_init(RTLIL::Module *mod, RTLIL::Process *proc) RTLIL::SigSpec lhs = action.first; RTLIL::SigSpec rhs = action.second; - lhs.optimize(); proc_get_const(rhs, proc->root_case); if (!rhs.is_fully_const()) diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index 9b8c3536..6949b76d 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -53,8 +53,6 @@ struct BruteForceEquivChecker return; } - inputs.optimize(); - ConstEval ce1(mod1), ce2(mod2); ce1.set(mod1_inputs, inputs.as_const()); ce2.set(mod2_inputs, inputs.as_const()); @@ -482,7 +480,6 @@ struct EvalPass : public Pass { RTLIL::SigSpec signal, value, undef; if (!RTLIL::SigSpec::parse_sel(signal, design, module, it)) log_cmd_error("Failed to parse show expression `%s'.\n", it.c_str()); - signal.optimize(); value = signal; if (set_undef) { while (!ce.eval(value, undef)) { diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index 1e47e7de..ba01bc32 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -349,7 +349,7 @@ struct PerformReduction std::vector bucket_sigbits; for (int idx : bucket) bucket_sigbits.push_back(out_bits[idx]); - log("%s Trying to shatter bucket with %d signals: %s\n", indt, int(bucket.size()), log_signal(RTLIL::SigSpec(bucket_sigbits).optimized())); + log("%s Trying to shatter bucket with %d signals: %s\n", indt, int(bucket.size()), log_signal(bucket_sigbits)); } std::vector sat_set_list, sat_clr_list; @@ -494,7 +494,7 @@ struct PerformReduction std::vector r_sigbits; for (int idx : r) r_sigbits.push_back(out_bits[idx]); - log(" Found group of %d equivialent signals: %s\n", int(r.size()), log_signal(RTLIL::SigSpec(r_sigbits).optimized())); + log(" Found group of %d equivialent signals: %s\n", int(r.size()), log_signal(r_sigbits)); } std::vector undef_slaves; @@ -640,7 +640,7 @@ struct FreduceWorker found_selected_wire: log(" Finding reduced input cone for signal batch %s%c\n", - log_signal(RTLIL::SigSpec(std::vector(batch.begin(), batch.end())).optimized()), verbose_level ? ':' : '.'); + log_signal(batch), verbose_level ? ':' : '.'); FindReducedInputs infinder(sigmap, drivers); for (auto &bit : batch) { @@ -663,12 +663,12 @@ struct FreduceWorker continue; if (bucket.first.size() == 0) { - log(" Finding const values for bucket %s%c\n", log_signal(RTLIL::SigSpec(bucket.second).optimized()), verbose_level ? ':' : '.'); + log(" Finding const values for bucket %s%c\n", log_signal(bucket.second), verbose_level ? ':' : '.'); PerformReduction worker(sigmap, drivers, inv_pairs, bucket.second, bucket.first.size()); for (size_t idx = 0; idx < bucket.second.size(); idx++) worker.analyze_const(equiv, idx); } else { - log(" Trying to shatter bucket %s%c\n", log_signal(RTLIL::SigSpec(bucket.second).optimized()), verbose_level ? ':' : '.'); + log(" Trying to shatter bucket %s%c\n", log_signal(bucket.second), verbose_level ? ':' : '.'); PerformReduction worker(sigmap, drivers, inv_pairs, bucket.second, bucket.first.size()); worker.analyze(equiv, 100 * bucket_count / (buckets.size() + 1)); } diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 34becaee..4b6b1b71 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -114,10 +114,6 @@ struct SatHelper } } - lhs.optimize(); - rhs.optimize(); - removed_bits.optimize(); - if (removed_bits.size()) log("Warning: ignoring initial value on non-register: %s\n", log_signal(removed_bits)); @@ -152,7 +148,6 @@ struct SatHelper if (!satgen.initial_state.check_all(big_lhs)) { RTLIL::SigSpec rem = satgen.initial_state.remove(big_lhs); - rem.optimize(); log_cmd_error("Found -set-init bits that are not part of the initial_state: %s\n", log_signal(rem)); } -- cgit v1.2.3