From a7e43ae3d97ef14c8d624d8fdfe938ae9f47ce84 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 3 Jan 2015 10:57:01 +0100 Subject: Progress in memory_bram --- techlibs/common/simlib.v | 3 +++ 1 file changed, 3 insertions(+) (limited to 'techlibs/common/simlib.v') diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 4680e209..f16bd6bd 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1540,6 +1540,9 @@ function port_active; endfunction always @(RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA) begin +`ifdef SIMLIB_MEMDELAY + #`SIMLIB_MEMDELAY; +`endif for (i = 0; i < RD_PORTS; i = i+1) begin if ((!RD_TRANSPARENT[i] && RD_CLK_ENABLE[i]) && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) RD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]; -- cgit v1.2.3