From fefe0fc0430f4f173a25e674708aa0f4f0854b31 Mon Sep 17 00:00:00 2001 From: Ruben Undheim Date: Thu, 3 Nov 2016 23:18:00 +0100 Subject: Imported yosys 0.7 --- techlibs/common/simlib.v | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'techlibs/common/simlib.v') diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 922a47ca..2c4db1ac 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1334,6 +1334,18 @@ endmodule // -------------------------------------------------------- +module \$anyseq (Y); + +parameter WIDTH = 0; + +output [WIDTH-1:0] Y; + +assign Y = 'bx; + +endmodule + +// -------------------------------------------------------- + module \$equiv (A, B, Y); input A, B; @@ -1380,6 +1392,23 @@ endgenerate endmodule +`endif +// -------------------------------------------------------- +`ifdef SIMLIB_FF + +module \$ff (D, Q); + +parameter WIDTH = 0; + +input [WIDTH-1:0] D; +output reg [WIDTH-1:0] Q; + +always @($global_clk) begin + Q <= D; +end + +endmodule + `endif // -------------------------------------------------------- -- cgit v1.2.3