From bedd46338fecd93c4c1c3b35017c26b080a990dc Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 30 Jan 2015 22:46:53 +0100 Subject: Added "fsm -encfile" --- techlibs/common/synth.cc | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) (limited to 'techlibs/common/synth.cc') diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc index 211b5905..5267344b 100644 --- a/techlibs/common/synth.cc +++ b/techlibs/common/synth.cc @@ -52,6 +52,9 @@ struct SynthPass : public Pass { log(" -top \n"); log(" use the specified module as top module (default='top')\n"); log("\n"); + log(" -encfile \n"); + log(" passed to 'fsm_recode' via 'fsm'\n"); + log("\n"); log(" -run [:]\n"); log(" only run the commands between the labels (see below). an empty\n"); log(" from label is synonymous to 'begin', and empty to label is\n"); @@ -91,7 +94,7 @@ struct SynthPass : public Pass { } virtual void execute(std::vector args, RTLIL::Design *design) { - std::string top_module; + std::string top_module, fsm_opts; std::string run_from, run_to; size_t argidx; @@ -101,6 +104,10 @@ struct SynthPass : public Pass { top_module = args[++argidx]; continue; } + if (args[argidx] == "-encfile" && argidx+1 < args.size()) { + fsm_opts = " -encfile " + args[++argidx]; + continue; + } if (args[argidx] == "-run" && argidx+1 < args.size()) { size_t pos = args[argidx+1].find(':'); if (pos == std::string::npos) { @@ -140,7 +147,7 @@ struct SynthPass : public Pass { Pass::call(design, "alumacc"); Pass::call(design, "share"); Pass::call(design, "opt"); - Pass::call(design, "fsm"); + Pass::call(design, "fsm" + fsm_opts); Pass::call(design, "opt -fast"); Pass::call(design, "memory -nomap"); Pass::call(design, "opt_clean"); -- cgit v1.2.3