From 1e67099b77904802880ad7c53d2cac33c6df456f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 19 Jan 2014 14:03:40 +0100 Subject: Added $assert cell --- techlibs/common/simlib.v | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'techlibs/common') diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 0e041e12..8f354a63 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -733,6 +733,21 @@ endmodule // -------------------------------------------------------- +module \$assert (A, EN); + +input A, EN; + +always @* begin + if (A !== 1'b1 && EN === 1'b1) begin + $display("Assertation failed!"); + $finish; + end +end + +endmodule + +// -------------------------------------------------------- + module \$sr (SET, CLR, Q); parameter WIDTH = 0; -- cgit v1.2.3