From 90f4017703a275c1a32cb347e4b60bd43873bbce Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 2 Jan 2015 22:45:26 +0100 Subject: Added proper clkpol support to memory_bram --- techlibs/common/simlib.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs/common') diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index ca4b1d36..4680e209 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1539,7 +1539,7 @@ function port_active; end endfunction -always @* begin +always @(RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA) begin for (i = 0; i < RD_PORTS; i = i+1) begin if ((!RD_TRANSPARENT[i] && RD_CLK_ENABLE[i]) && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) RD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]; -- cgit v1.2.3