From fc3b3c4ec3955b165166d9f44965fac0e1879505 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 7 Feb 2014 17:44:57 +0100
Subject: Added $slice and $concat cell types

---
 techlibs/common/simlib.v   | 30 ++++++++++++++++++++++++++++++
 techlibs/common/stdcells.v | 12 ++++++++++++
 2 files changed, 42 insertions(+)

(limited to 'techlibs/common')

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 87e83bd1..4436abfe 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -829,6 +829,36 @@ endmodule
 
 // --------------------------------------------------------
 
+module \$slice (A, Y);
+
+parameter OFFSET = 0;
+parameter A_WIDTH = 0;
+parameter Y_WIDTH = 0;
+
+input [A_WIDTH-1:0] A;
+output [Y_WIDTH-1:0] Y;
+
+assign Y = A >> OFFSET;
+
+endmodule
+
+// --------------------------------------------------------
+
+module \$concat (A, B, Y);
+
+parameter A_WIDTH = 0;
+parameter B_WIDTH = 0;
+
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
+output [A_WIDTH+B_WIDTH-1:0] Y;
+
+assign Y = {B, A};
+
+endmodule
+
+// --------------------------------------------------------
+
 module \$mux (A, B, S, Y);
 
 parameter WIDTH = 0;
diff --git a/techlibs/common/stdcells.v b/techlibs/common/stdcells.v
index e33e651c..fdee26b6 100644
--- a/techlibs/common/stdcells.v
+++ b/techlibs/common/stdcells.v
@@ -956,6 +956,18 @@ endmodule
 
 // --------------------------------------------------------
 
+(* techmap_simplemap *)
+module \$slice ;
+endmodule
+
+// --------------------------------------------------------
+
+(* techmap_simplemap *)
+module \$concat ;
+endmodule
+
+// --------------------------------------------------------
+
 (* techmap_simplemap *)
 module \$mux ;
 endmodule
-- 
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