From fefe0fc0430f4f173a25e674708aa0f4f0854b31 Mon Sep 17 00:00:00 2001 From: Ruben Undheim Date: Thu, 3 Nov 2016 23:18:00 +0100 Subject: Imported yosys 0.7 --- techlibs/gowin/cells_sim.v | 51 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 techlibs/gowin/cells_sim.v (limited to 'techlibs/gowin/cells_sim.v') diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v new file mode 100644 index 00000000..3a09c157 --- /dev/null +++ b/techlibs/gowin/cells_sim.v @@ -0,0 +1,51 @@ +module LUT1(output F, input I0); + parameter [1:0] INIT = 0; + assign F = I0 ? INIT[1] : INIT[0]; +endmodule + +module LUT2(output F, input I0, I1); + parameter [3:0] INIT = 0; + wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0]; + assign F = I0 ? s1[1] : s1[0]; +endmodule + +module LUT3(output F, input I0, I1, I2); + parameter [7:0] INIT = 0; + wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0]; + wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; + assign F = I0 ? s1[1] : s1[0]; +endmodule + +module LUT4(output F, input I0, I1, I2, I3); + parameter [15:0] INIT = 0; + wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0]; + wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; + wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; + assign F = I0 ? s1[1] : s1[0]; +endmodule + +module DFF (output reg Q, input CLK, D); + always @(posedge C) + Q <= D; +endmodule + +module DFFN (output reg Q, input CLK, D); + always @(negedge C) + Q <= D; +endmodule + +module VCC(output V); + assign V = 1; +endmodule + +module GND(output G); + assign G = 0; +endmodule + +module IBUF(output O, input I); + assign O = I; +endmodule + +module OBUF(output O, input I); + assign O = I; +endmodule -- cgit v1.2.3