From ff5734b20220e6fb4a3913cf5279ed94bb5156ea Mon Sep 17 00:00:00 2001 From: Ruben Undheim Date: Thu, 28 Mar 2019 23:35:03 +0100 Subject: Imported GIT HEAD: 0.8+20190328git32bd0f2 --- techlibs/gowin/Makefile.inc | 1 + techlibs/gowin/arith_map.v | 59 +++++++++++++++++++++++++++++++++++++++++++ techlibs/gowin/cells_sim.v | 6 +++++ techlibs/gowin/synth_gowin.cc | 31 +++++++++++++++++++---- 4 files changed, 92 insertions(+), 5 deletions(-) create mode 100644 techlibs/gowin/arith_map.v (limited to 'techlibs/gowin') diff --git a/techlibs/gowin/Makefile.inc b/techlibs/gowin/Makefile.inc index 679d7eff..2f82def7 100644 --- a/techlibs/gowin/Makefile.inc +++ b/techlibs/gowin/Makefile.inc @@ -3,4 +3,5 @@ OBJS += techlibs/gowin/synth_gowin.o $(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_map.v)) $(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_sim.v)) +$(eval $(call add_share_file,share/gowin,techlibs/gowin/arith_map.v)) diff --git a/techlibs/gowin/arith_map.v b/techlibs/gowin/arith_map.v new file mode 100644 index 00000000..e15de642 --- /dev/null +++ b/techlibs/gowin/arith_map.v @@ -0,0 +1,59 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * Copyright (C) 2018 David Shah + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +(* techmap_celltype = "$alu" *) +module _80_gw1n_alu(A, B, CI, BI, X, Y, CO); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 1; + parameter B_WIDTH = 1; + parameter Y_WIDTH = 1; + + input [A_WIDTH-1:0] A; + input [B_WIDTH-1:0] B; + output [Y_WIDTH-1:0] X, Y; + + input CI, BI; + output [Y_WIDTH-1:0] CO; + + wire _TECHMAP_FAIL_ = Y_WIDTH <= 2; + + wire [Y_WIDTH-1:0] A_buf, B_buf; + \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); + \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); + + wire [Y_WIDTH-1:0] AA = A_buf; + wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; + wire [Y_WIDTH-1:0] C = {CO, CI}; + + genvar i; + generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice + ALU #(.ALU_MODE(32'b0)) + alu(.I0(AA[i]), + .I1(BB[i]), + .I3(1'b0), + .CIN(C[i]), + .COUT(CO[i]), + .SUM(Y[i]) + ); + end endgenerate + assign X = AA ^ BB; +endmodule + diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v index 94794262..14441c2f 100644 --- a/techlibs/gowin/cells_sim.v +++ b/techlibs/gowin/cells_sim.v @@ -57,3 +57,9 @@ endmodule module GSR (input GSRI); wire GSRO = GSRI; endmodule + +module ALU (input I0, input I1, input I3, input CIN, output COUT, output SUM); + parameter [3:0] ALU_MODE = 0; // default 0 = ADD + assign {COUT, SUM} = CIN + I1 + I0; +endmodule // alu + diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index 793f345b..9a3fcdbb 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -49,6 +49,12 @@ struct SynthGowinPass : public ScriptPass log(" from label is synonymous to 'begin', and empty to label is\n"); log(" synonymous to the end of the command list.\n"); log("\n"); + log(" -nobram\n"); + log(" do not use BRAM cells in output netlist\n"); + log("\n"); + log(" -noflatten\n"); + log(" do not flatten design before synthesis\n"); + log("\n"); log(" -retime\n"); log(" run 'abc' with -dff option\n"); log("\n"); @@ -59,13 +65,15 @@ struct SynthGowinPass : public ScriptPass } string top_opt, vout_file; - bool retime; + bool retime, flatten, nobram; void clear_flags() YS_OVERRIDE { top_opt = "-auto-top"; vout_file = ""; retime = false; + flatten = true; + nobram = true; } void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE @@ -96,12 +104,20 @@ struct SynthGowinPass : public ScriptPass retime = true; continue; } + if (args[argidx] == "-nobram") { + nobram = true; + continue; + } + if (args[argidx] == "-noflatten") { + flatten = false; + continue; + } break; } extra_args(args, argidx, design); if (!design->full_selection()) - log_cmd_error("This comannd only operates on fully selected designs!\n"); + log_cmd_error("This command only operates on fully selected designs!\n"); log_header(design, "Executing SYNTH_GOWIN pass.\n"); log_push(); @@ -119,7 +135,7 @@ struct SynthGowinPass : public ScriptPass run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); } - if (check_label("flatten")) + if (flatten && check_label("flatten", "(unless -noflatten)")) { run("proc"); run("flatten"); @@ -131,13 +147,18 @@ struct SynthGowinPass : public ScriptPass { run("synth -run coarse"); } - + if (!nobram && check_label("bram", "(skip if -nobram)")) + { + run("memory_bram -rules +/gowin/bram.txt"); + run("techmap -map +/gowin/brams_map.v"); + } if (check_label("fine")) { run("opt -fast -mux_undef -undriven -fine"); run("memory_map"); run("opt -undriven -fine"); - run("techmap"); + run("techmap -map +/techmap.v -map +/gowin/arith_map.v"); + run("opt -fine"); run("clean -purge"); run("splitnets -ports"); run("setundef -undriven -zero"); -- cgit v1.2.3