From 0ccfb88728c5bdf167b1d672034ca5cf360dedb1 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 7 Feb 2016 11:19:48 +0100 Subject: Work around DDR dout sim glitches in ice40 SB_IO sim model --- techlibs/ice40/cells_sim.v | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'techlibs/ice40/cells_sim.v') diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index f23218c0..7778b551 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -47,11 +47,17 @@ module SB_IO ( din_1 = din_q_1; end + // work around simulation glitches on dout in DDR mode + reg outclk_delayed_1; + reg outclk_delayed_2; + always @* outclk_delayed_1 <= OUTPUT_CLK; + always @* outclk_delayed_2 <= outclk_delayed_1; + always @* begin if (PIN_TYPE[3]) dout = PIN_TYPE[2] ? !dout_q_0 : D_OUT_0; else - dout = (OUTPUT_CLK ^ NEG_TRIGGER) || PIN_TYPE[2] ? dout_q_0 : dout_q_1; + dout = (outclk_delayed_2 ^ NEG_TRIGGER) || PIN_TYPE[2] ? dout_q_0 : dout_q_1; end assign D_IN_0 = din_0, D_IN_1 = din_1; -- cgit v1.2.3