From 11789db206276edf50f45f8d82e094a87643630c Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 14 Mar 2013 11:15:00 +0100
Subject: More support code for $sr cells

---
 techlibs/simlib.v | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

(limited to 'techlibs/simlib.v')

diff --git a/techlibs/simlib.v b/techlibs/simlib.v
index 17924254..29c13503 100644
--- a/techlibs/simlib.v
+++ b/techlibs/simlib.v
@@ -642,6 +642,27 @@ endmodule
 
 // --------------------------------------------------------
 
+module \$sr (S, R, Q);
+
+parameter WIDTH = 0;
+
+input CLK;
+input [WIDTH-1:0] S, R;
+output reg [WIDTH-1:0] Q;
+
+integer i;
+always @(S, R)
+	for (i = 0; i < WIDTH; i = i+1) begin
+		if (R[i])
+			Q[i] <= 0;
+		else if (S[i])
+			Q[i] <= 1;
+	end
+
+endmodule
+
+// --------------------------------------------------------
+
 module \$dff (CLK, D, Q);
 
 parameter WIDTH = 0;
-- 
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