From 32dbf7752d5ae41966bf19773bf8561b538fe8f0 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 7 Apr 2013 16:42:29 +0200 Subject: Fixed clock related parameter names for $memrd and $memwr in techlibs/simlib.v --- techlibs/simlib.v | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'techlibs/simlib.v') diff --git a/techlibs/simlib.v b/techlibs/simlib.v index 8675a4d0..ff988cbe 100644 --- a/techlibs/simlib.v +++ b/techlibs/simlib.v @@ -799,8 +799,8 @@ parameter MEMID = ""; parameter ABITS = 8; parameter WIDTH = 8; -parameter RD_CLK_ENABLE = 0; -parameter RD_CLK_POLARITY = 0; +parameter CLK_ENABLE = 0; +parameter CLK_POLARITY = 0; input CLK; input [ABITS-1:0] ADDR; @@ -821,8 +821,8 @@ parameter MEMID = ""; parameter ABITS = 8; parameter WIDTH = 8; -parameter RD_CLK_ENABLE = 0; -parameter RD_CLK_POLARITY = 0; +parameter CLK_ENABLE = 0; +parameter CLK_POLARITY = 0; input CLK, EN; input [ABITS-1:0] ADDR; -- cgit v1.2.3