From 4389d9306ecb64df29115027ad9a948d852448bd Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 6 Apr 2015 08:44:30 +0200 Subject: Added Xilinx bram black-box modules --- techlibs/xilinx/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'techlibs/xilinx/Makefile.inc') diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index 9af7b58f..18f6764e 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -5,5 +5,6 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_sim.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams.txt)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_map.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_bb.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v)) -- cgit v1.2.3