From 532091afcbb8ba547392f51ba3a020d993e099da Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 23 Nov 2013 15:58:06 +0100 Subject: Added more generic _TECHMAP_ wire mechanism to techmap pass --- techlibs/xilinx/cells.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs/xilinx/cells.v') diff --git a/techlibs/xilinx/cells.v b/techlibs/xilinx/cells.v index 8c8b9c75..5bf8ccd8 100644 --- a/techlibs/xilinx/cells.v +++ b/techlibs/xilinx/cells.v @@ -46,7 +46,7 @@ module \$lut (I, O); .I0(I[0]), .I1(I[1]), .I2(I[2]), .I3(I[3]), .I4(I[4]), .I5(I[5])); end else begin:error - wire TECHMAP_FAIL; + wire _TECHMAP_FAIL_ = 1; end endgenerate -- cgit v1.2.3