From 7b99a3646c44759b82d7df0361d59c72776b8aed Mon Sep 17 00:00:00 2001 From: Ruben Undheim Date: Mon, 15 Oct 2018 23:51:39 +0200 Subject: New upstream version 0.7+20181007git9850de4 --- techlibs/xilinx/cells_xtra.v | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'techlibs/xilinx/cells_xtra.v') diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v index a2dd01ad..69e54233 100644 --- a/techlibs/xilinx/cells_xtra.v +++ b/techlibs/xilinx/cells_xtra.v @@ -2225,6 +2225,7 @@ module IOBUF (...); parameter IOSTANDARD = "DEFAULT"; parameter SLEW = "SLOW"; output O; + inout IO; input I, T; endmodule @@ -2236,6 +2237,7 @@ module IOBUF_DCIEN (...); parameter SLEW = "SLOW"; parameter USE_IBUFDISABLE = "TRUE"; output O; + inout IO; input DCITERMDISABLE; input I; input IBUFDISABLE; @@ -2250,6 +2252,7 @@ module IOBUF_INTERMDISABLE (...); parameter SLEW = "SLOW"; parameter USE_IBUFDISABLE = "TRUE"; output O; + inout IO; input I; input IBUFDISABLE; input INTERMDISABLE; @@ -2263,6 +2266,7 @@ module IOBUFDS (...); parameter IOSTANDARD = "DEFAULT"; parameter SLEW = "SLOW"; output O; + inout IO, IOB; input I, T; endmodule @@ -2275,6 +2279,8 @@ module IOBUFDS_DCIEN (...); parameter SLEW = "SLOW"; parameter USE_IBUFDISABLE = "TRUE"; output O; + inout IO; + inout IOB; input DCITERMDISABLE; input I; input IBUFDISABLE; @@ -2288,6 +2294,8 @@ module IOBUFDS_DIFF_OUT (...); parameter IOSTANDARD = "DEFAULT"; output O; output OB; + inout IO; + inout IOB; input I; input TM; input TS; @@ -2302,6 +2310,8 @@ module IOBUFDS_DIFF_OUT_DCIEN (...); parameter USE_IBUFDISABLE = "TRUE"; output O; output OB; + inout IO; + inout IOB; input DCITERMDISABLE; input I; input IBUFDISABLE; @@ -2318,6 +2328,8 @@ module IOBUFDS_DIFF_OUT_INTERMDISABLE (...); parameter USE_IBUFDISABLE = "TRUE"; output O; output OB; + inout IO; + inout IOB; input I; input IBUFDISABLE; input INTERMDISABLE; @@ -2381,6 +2393,7 @@ module ISERDESE2 (...); endmodule module KEEPER (...); + inout O; endmodule module LDCE (...); -- cgit v1.2.3