From 88cd2eadf5f889eb0187f25789a9e6bd95ccdb7b Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 27 Oct 2013 09:52:00 +0100
Subject: Cleanups in xilinx examples

---
 techlibs/xilinx/example_sim_counter/run_sim.sh     | 23 ++++++
 .../xilinx/example_sim_counter/run_testbench.sh    | 86 ----------------------
 2 files changed, 23 insertions(+), 86 deletions(-)
 create mode 100644 techlibs/xilinx/example_sim_counter/run_sim.sh
 delete mode 100644 techlibs/xilinx/example_sim_counter/run_testbench.sh

(limited to 'techlibs/xilinx/example_sim_counter')

diff --git a/techlibs/xilinx/example_sim_counter/run_sim.sh b/techlibs/xilinx/example_sim_counter/run_sim.sh
new file mode 100644
index 00000000..e26d00db
--- /dev/null
+++ b/techlibs/xilinx/example_sim_counter/run_sim.sh
@@ -0,0 +1,23 @@
+#!/bin/bash
+
+set -ex
+
+XILINX_DIR=/opt/Xilinx/14.5/ISE_DS/ISE
+
+../../../yosys -p 'synth_xilinx -top counter; write_verilog -noattr testbench_synth.v' counter.v
+
+iverilog -o testbench_gold counter_tb.v counter.v
+iverilog -o testbench_gate counter_tb.v testbench_synth.v \
+	$XILINX_DIR/verilog/src/{glbl,unisims/{FDRE,LUT1,LUT2,LUT3,LUT4,LUT5,LUT6}}.v
+
+./testbench_gold > testbench_gold.txt
+./testbench_gate > testbench_gate.txt
+
+if diff -u testbench_gold.txt testbench_gate.txt; then
+	set +x; echo; echo; banner "  PASS  "
+else
+	exit 1
+fi
+
+rm -f testbench_{synth,gold,gate,mapped}*
+
diff --git a/techlibs/xilinx/example_sim_counter/run_testbench.sh b/techlibs/xilinx/example_sim_counter/run_testbench.sh
deleted file mode 100644
index b4251f49..00000000
--- a/techlibs/xilinx/example_sim_counter/run_testbench.sh
+++ /dev/null
@@ -1,86 +0,0 @@
-#!/bin/bash
-
-set -ex
-
-XILINX_DIR=/opt/Xilinx/14.2/ISE_DS/ISE/
-
-../../yosys - <<- EOT
-	# read design
-	read_verilog counter.v
-
-	# high-level synthesis
-	hierarchy -check -top counter
-	proc; opt; fsm; opt; techmap; opt
-
-	# mapping logic to LUTs using Berkeley ABC
-	abc -lut 6; opt
-
-	# map internal cells to FPGA cells
-	techmap -map cells.v; opt
-
-	# write netlist
-	write_verilog -noattr testbench_synth.v
-	write_edif testbench_synth.edif
-EOT
-
-iverilog -o testbench_gold counter_tb.v counter.v
-iverilog -o testbench_gate counter_tb.v testbench_synth.v \
-	$XILINX_DIR/verilog/src/{glbl,unisims/{FDRE,LUT1,LUT2,LUT3,LUT4,LUT5,LUT6}}.v
-
-./testbench_gold > testbench_gold.txt
-./testbench_gate > testbench_gate.txt
-
-if diff -u testbench_gold.txt testbench_gate.txt; then
-	set +x; echo; echo; banner "  PASS  "
-else
-	exit 1
-fi
-
-if [ "$*" = "-map" ]; then
-	set -x
-
-	cat > testbench_synth.ut <<- EOT
-		-w
-		-g DebugBitstream:No
-		-g Binary:no
-		-g CRC:Enable
-		-g Reset_on_err:No
-		-g ConfigRate:2
-		-g ProgPin:PullUp
-		-g TckPin:PullUp
-		-g TdiPin:PullUp
-		-g TdoPin:PullUp
-		-g TmsPin:PullUp
-		-g UnusedPin:PullDown
-		-g UserID:0xFFFFFFFF
-		-g ExtMasterCclk_en:No
-		-g SPI_buswidth:1
-		-g TIMER_CFG:0xFFFF
-		-g multipin_wakeup:No
-		-g StartUpClk:CClk
-		-g DONE_cycle:4
-		-g GTS_cycle:5
-		-g GWE_cycle:6
-		-g LCK_cycle:NoWait
-		-g Security:None
-		-g DonePipe:No
-		-g DriveDone:No
-		-g en_sw_gsr:No
-		-g drive_awake:No
-		-g sw_clk:Startupclk
-		-g sw_gwe_cycle:5
-		-g sw_gts_cycle:4
-	EOT
-
-	$XILINX_DIR/bin/lin64/edif2ngd testbench_synth.edif
-	$XILINX_DIR/bin/lin64/ngdbuild -p xc7k70t testbench_synth
-	$XILINX_DIR/bin/lin64/map -p xc7k70t-fbg676-1 -w -o testbench_mapped.ncd testbench_synth prffile.pcf
-	$XILINX_DIR/bin/lin64/par -w testbench_mapped.ncd testbench_synth.ncd prffile.pcf
-	$XILINX_DIR/bin/lin64/bitgen -f testbench_synth.ut testbench_synth.ncd
-fi
-
-if [ "$*" = "-clean" ]; then
-	rm -rf netlist.lst _xmsgs/ prffile.pcf
-	rm -f testbench_{synth,gold,gate,mapped}*
-fi
-
-- 
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