From 9ea2511fe87a9a3a4dd179101f42982ed62e78c0 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 5 Jan 2015 13:59:04 +0100 Subject: Towards Xilinx bram support --- techlibs/xilinx/tests/bram1.v | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 techlibs/xilinx/tests/bram1.v (limited to 'techlibs/xilinx/tests/bram1.v') diff --git a/techlibs/xilinx/tests/bram1.v b/techlibs/xilinx/tests/bram1.v new file mode 100644 index 00000000..034cc18e --- /dev/null +++ b/techlibs/xilinx/tests/bram1.v @@ -0,0 +1,24 @@ +module bram1 #( + parameter ABITS = 8, DBITS = 8, TRANSP = 0 +) ( + input clk, + + input [ABITS-1:0] WR_ADDR, + input [DBITS-1:0] WR_DATA, + input WR_EN, + + input [ABITS-1:0] RD_ADDR, + output [DBITS-1:0] RD_DATA +); + reg [DBITS-1:0] memory [0:2**ABITS-1]; + reg [ABITS-1:0] RD_ADDR_BUF; + reg [DBITS-1:0] RD_DATA_BUF; + + always @(posedge clk) begin + if (WR_EN) memory[WR_ADDR] <= WR_DATA; + RD_ADDR_BUF <= RD_ADDR; + RD_DATA_BUF <= memory[RD_ADDR]; + end + + assign RD_DATA = TRANSP ? memory[RD_ADDR_BUF] : RD_DATA_BUF; +endmodule -- cgit v1.2.3