From 8520b7fbe0b24dda47749aa870881b6b03480d4a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 6 Apr 2015 17:07:10 +0200 Subject: Added support for initialized xilinx brams --- techlibs/xilinx/tests/bram2.v | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) (limited to 'techlibs/xilinx/tests/bram2.v') diff --git a/techlibs/xilinx/tests/bram2.v b/techlibs/xilinx/tests/bram2.v index 9444fb17..0a6013ca 100644 --- a/techlibs/xilinx/tests/bram2.v +++ b/techlibs/xilinx/tests/bram2.v @@ -1,18 +1,29 @@ module myram( input rd_clk, input [ 7:0] rd_addr, - output reg [15:0] rd_data, + output reg [17:0] rd_data, input wr_clk, input wr_enable, input [ 7:0] wr_addr, - input [15:0] wr_data + input [17:0] wr_data ); - reg [15:0] memory [0:255]; + reg [17:0] memory [0:255]; integer i; + function [17:0] hash(input [7:0] k); + reg [31:0] x; + begin + x = {k, ~k, k, ~k}; + x = x ^ (x << 13); + x = x ^ (x >> 17); + x = x ^ (x << 5); + hash = x; + end + endfunction + initial begin for (i = 0; i < 256; i = i+1) - memory[i] = i; + memory[i] = hash(i); end always @(posedge rd_clk) -- cgit v1.2.3