From 5033b51947a6ef02cb785b5622e993335efa750a Mon Sep 17 00:00:00 2001 From: Ruben Undheim Date: Thu, 30 Aug 2018 20:46:20 +0200 Subject: New upstream version 0.7+20180830git0b7a184 --- techlibs/xilinx/Makefile.inc | 2 +- techlibs/xilinx/brams_init.py | 16 +++++----- techlibs/xilinx/cells_map.v | 2 ++ techlibs/xilinx/cells_sim.v | 30 +++++++++++++++++++ techlibs/xilinx/drams_bb.v | 20 ------------- techlibs/xilinx/lut2lut.v | 65 +++++++++++++++++++++++++++++++++++++++++ techlibs/xilinx/synth_xilinx.cc | 43 ++++++++++++++++++++++----- 7 files changed, 142 insertions(+), 36 deletions(-) delete mode 100644 techlibs/xilinx/drams_bb.v create mode 100644 techlibs/xilinx/lut2lut.v (limited to 'techlibs/xilinx') diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index 5f09ffb0..887ea27d 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -27,8 +27,8 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_bb.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams.txt)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_map.v)) -$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_bb.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut2lut.v)) $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_36.vh)) $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_32.vh)) diff --git a/techlibs/xilinx/brams_init.py b/techlibs/xilinx/brams_init.py index e787b1f7..d46a2b4f 100644 --- a/techlibs/xilinx/brams_init.py +++ b/techlibs/xilinx/brams_init.py @@ -2,27 +2,27 @@ with open("techlibs/xilinx/brams_init_18.vh", "w") as f: for i in range(8): - init_snippets = ["INIT[%3d*9+8]" % (k+256*i,) for k in range(255, -1, -1)] + init_snippets = [" INIT[%3d*9+8]" % (k+256*i,) for k in range(255, -1, -1)] for k in range(4, 256, 4): init_snippets[k] = "\n " + init_snippets[k] - print(".INITP_%02X({%s})," % (i, ", ".join(init_snippets)), file=f) + print(".INITP_%02X({%s})," % (i, ",".join(init_snippets)), file=f) for i in range(64): - init_snippets = ["INIT[%3d*9 +: 8]" % (k+32*i,) for k in range(31, -1, -1)] + init_snippets = [" INIT[%3d*9 +: 8]" % (k+32*i,) for k in range(31, -1, -1)] for k in range(4, 32, 4): init_snippets[k] = "\n " + init_snippets[k] - print(".INIT_%02X({%s})," % (i, ", ".join(init_snippets)), file=f) + print(".INIT_%02X({%s})," % (i, ",".join(init_snippets)), file=f) with open("techlibs/xilinx/brams_init_36.vh", "w") as f: for i in range(16): - init_snippets = ["INIT[%3d*9+8]" % (k+256*i,) for k in range(255, -1, -1)] + init_snippets = [" INIT[%3d*9+8]" % (k+256*i,) for k in range(255, -1, -1)] for k in range(4, 256, 4): init_snippets[k] = "\n " + init_snippets[k] - print(".INITP_%02X({%s})," % (i, ", ".join(init_snippets)), file=f) + print(".INITP_%02X({%s})," % (i, ",".join(init_snippets)), file=f) for i in range(128): - init_snippets = ["INIT[%3d*9 +: 8]" % (k+32*i,) for k in range(31, -1, -1)] + init_snippets = [" INIT[%3d*9 +: 8]" % (k+32*i,) for k in range(31, -1, -1)] for k in range(4, 32, 4): init_snippets[k] = "\n " + init_snippets[k] - print(".INIT_%02X({%s})," % (i, ", ".join(init_snippets)), file=f) + print(".INIT_%02X({%s})," % (i, ",".join(init_snippets)), file=f) with open("techlibs/xilinx/brams_init_16.vh", "w") as f: for i in range(64): diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 8e5a83ce..0771be0b 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -15,6 +15,7 @@ module \$_DFF_NP1_ (input D, C, R, output Q); FDPE #(.INIT(|0), .IS_C_INVERTED( module \$_DFF_PN1_ (input D, C, R, output Q); FDPE #(.INIT(|0), .IS_C_INVERTED(|0), .IS_D_INVERTED(|0), .IS_PRE_INVERTED(|1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(R)); endmodule module \$_DFF_PP1_ (input D, C, R, output Q); FDPE #(.INIT(|0), .IS_C_INVERTED(|0), .IS_D_INVERTED(|0), .IS_PRE_INVERTED(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(R)); endmodule +`ifndef NO_LUT module \$lut (A, Y); parameter WIDTH = 0; parameter LUT = 0; @@ -82,3 +83,4 @@ module \$lut (A, Y); end endgenerate endmodule +`endif diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 1f114a22..eba17ac9 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -156,3 +156,33 @@ module FDPE (output reg Q, input C, CE, D, PRE); endcase endgenerate endmodule +module RAM64X1D ( + output DPO, SPO, + input D, WCLK, WE, + input A0, A1, A2, A3, A4, A5, + input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5 +); + parameter INIT = 64'h0; + parameter IS_WCLK_INVERTED = 1'b0; + wire [5:0] a = {A5, A4, A3, A2, A1, A0}; + wire [5:0] dpra = {DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}; + reg [63:0] mem = INIT; + assign SPO = mem[a]; + assign DPO = mem[dpra]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(posedge clk) if (WE) mem[a] <= D; +endmodule + +module RAM128X1D ( + output DPO, SPO, + input D, WCLK, WE, + input [6:0] A, DPRA +); + parameter INIT = 128'h0; + parameter IS_WCLK_INVERTED = 1'b0; + reg [127:0] mem = INIT; + assign SPO = mem[A]; + assign DPO = mem[DPRA]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(posedge clk) if (WE) mem[A] <= D; +endmodule diff --git a/techlibs/xilinx/drams_bb.v b/techlibs/xilinx/drams_bb.v deleted file mode 100644 index 11168fe1..00000000 --- a/techlibs/xilinx/drams_bb.v +++ /dev/null @@ -1,20 +0,0 @@ - -module RAM64X1D ( - output DPO, SPO, - input D, WCLK, WE, - input A0, A1, A2, A3, A4, A5, - input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5 -); - parameter INIT = 64'h0; - parameter IS_WCLK_INVERTED = 1'b0; -endmodule - -module RAM128X1D ( - output DPO, SPO, - input D, WCLK, WE, - input [6:0] A, DPRA -); - parameter INIT = 128'h0; - parameter IS_WCLK_INVERTED = 1'b0; -endmodule - diff --git a/techlibs/xilinx/lut2lut.v b/techlibs/xilinx/lut2lut.v new file mode 100644 index 00000000..061ad204 --- /dev/null +++ b/techlibs/xilinx/lut2lut.v @@ -0,0 +1,65 @@ +module LUT1(output O, input I0); + parameter [1:0] INIT = 0; + \$lut #( + .WIDTH(1), + .LUT(INIT) + ) _TECHMAP_REPLACE_ ( + .A(I0), + .Y(O) + ); +endmodule + +module LUT2(output O, input I0, I1); + parameter [3:0] INIT = 0; + \$lut #( + .WIDTH(2), + .LUT(INIT) + ) _TECHMAP_REPLACE_ ( + .A({I1, I0}), + .Y(O) + ); +endmodule + +module LUT3(output O, input I0, I1, I2); + parameter [7:0] INIT = 0; + \$lut #( + .WIDTH(3), + .LUT(INIT) + ) _TECHMAP_REPLACE_ ( + .A({I2, I1, I0}), + .Y(O) + ); +endmodule + +module LUT4(output O, input I0, I1, I2, I3); + parameter [15:0] INIT = 0; + \$lut #( + .WIDTH(4), + .LUT(INIT) + ) _TECHMAP_REPLACE_ ( + .A({I3, I2, I1, I0}), + .Y(O) + ); +endmodule + +module LUT5(output O, input I0, I1, I2, I3, I4); + parameter [31:0] INIT = 0; + \$lut #( + .WIDTH(5), + .LUT(INIT) + ) _TECHMAP_REPLACE_ ( + .A({I4, I3, I2, I1, I0}), + .Y(O) + ); +endmodule + +module LUT6(output O, input I0, I1, I2, I3, I4, I5); + parameter [63:0] INIT = 0; + \$lut #( + .WIDTH(6), + .LUT(INIT) + ) _TECHMAP_REPLACE_ ( + .A({I5, I4, I3, I2, I1, I0}), + .Y(O) + ); +endmodule diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index e7ec1e6e..590fe61d 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -34,9 +34,11 @@ bool check_label(bool &active, std::string run_from, std::string run_to, std::st return active; } -struct SynthXilinxPass : public Pass { +struct SynthXilinxPass : public Pass +{ SynthXilinxPass() : Pass("synth_xilinx", "synthesis for Xilinx FPGAs") { } - virtual void help() + + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -53,6 +55,14 @@ struct SynthXilinxPass : public Pass { log(" write the design to the specified edif file. writing of an output file\n"); log(" is omitted if this parameter is not specified.\n"); log("\n"); + log(" -blif \n"); + log(" write the design to the specified BLIF file. writing of an output file\n"); + log(" is omitted if this parameter is not specified.\n"); + log("\n"); + log(" -vpr\n"); + log(" generate an output netlist (and BLIF file) suitable for VPR\n"); + log(" (this feature is experimental and incomplete)\n"); + log("\n"); log(" -run :\n"); log(" only run the commands between the labels (see below). an empty\n"); log(" from label is synonymous to 'begin', and empty to label is\n"); @@ -71,7 +81,6 @@ struct SynthXilinxPass : public Pass { log(" read_verilog -lib +/xilinx/cells_sim.v\n"); log(" read_verilog -lib +/xilinx/cells_xtra.v\n"); log(" read_verilog -lib +/xilinx/brams_bb.v\n"); - log(" read_verilog -lib +/xilinx/drams_bb.v\n"); log(" hierarchy -check -top \n"); log("\n"); log(" flatten: (only if -flatten)\n"); @@ -103,7 +112,7 @@ struct SynthXilinxPass : public Pass { log(" clean\n"); log("\n"); log(" map_cells:\n"); - log(" techmap -map +/xilinx/cells_map.v\n"); + log(" techmap -map +/xilinx/cells_map.v (with -D NO_LUT in vpr mode)\n"); log(" dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT\n"); log(" clean\n"); log("\n"); @@ -115,14 +124,19 @@ struct SynthXilinxPass : public Pass { log(" edif: (only if -edif)\n"); log(" write_edif \n"); log("\n"); + log(" blif: (only if -blif)\n"); + log(" write_blif \n"); + log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { std::string top_opt = "-auto-top"; std::string edif_file; + std::string blif_file; std::string run_from, run_to; bool flatten = false; bool retime = false; + bool vpr = false; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) @@ -135,6 +149,10 @@ struct SynthXilinxPass : public Pass { edif_file = args[++argidx]; continue; } + if (args[argidx] == "-blif" && argidx+1 < args.size()) { + blif_file = args[++argidx]; + continue; + } if (args[argidx] == "-run" && argidx+1 < args.size()) { size_t pos = args[argidx+1].find(':'); if (pos == std::string::npos) @@ -151,6 +169,10 @@ struct SynthXilinxPass : public Pass { retime = true; continue; } + if (args[argidx] == "-vpr") { + vpr = true; + continue; + } break; } extra_args(args, argidx, design); @@ -168,7 +190,6 @@ struct SynthXilinxPass : public Pass { Pass::call(design, "read_verilog -lib +/xilinx/cells_sim.v"); Pass::call(design, "read_verilog -lib +/xilinx/cells_xtra.v"); Pass::call(design, "read_verilog -lib +/xilinx/brams_bb.v"); - Pass::call(design, "read_verilog -lib +/xilinx/drams_bb.v"); Pass::call(design, stringf("hierarchy -check %s", top_opt.c_str())); } @@ -214,7 +235,10 @@ struct SynthXilinxPass : public Pass { if (check_label(active, run_from, run_to, "map_cells")) { - Pass::call(design, "techmap -map +/xilinx/cells_map.v"); + if (vpr) + Pass::call(design, "techmap -D NO_LUT -map +/xilinx/cells_map.v"); + else + Pass::call(design, "techmap -map +/xilinx/cells_map.v"); Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT"); Pass::call(design, "clean"); } @@ -231,6 +255,11 @@ struct SynthXilinxPass : public Pass { if (!edif_file.empty()) Pass::call(design, stringf("write_edif %s", edif_file.c_str())); } + if (check_label(active, run_from, run_to, "blif")) + { + if (!blif_file.empty()) + Pass::call(design, stringf("write_blif %s", edif_file.c_str())); + } log_pop(); } -- cgit v1.2.3