From 864808992be407a9b33f222fa5846f5cd5f149ea Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 30 Oct 2015 13:58:03 +0100 Subject: Bugfix in Xilinx LUT mapping --- techlibs/xilinx/synth_xilinx.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs/xilinx') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index ee67beba..fbcc9601 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -204,7 +204,7 @@ struct SynthXilinxPass : public Pass { if (check_label(active, run_from, run_to, "map_luts")) { - Pass::call(design, "abc -lut 5:8" + string(retime ? " -dff" : "")); + Pass::call(design, "abc -lut 6:8" + string(retime ? " -dff" : "")); Pass::call(design, "clean"); } -- cgit v1.2.3