From 17372d8abde0139df4b8df3ebbeb71b222157200 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 1 Feb 2016 12:40:32 +0100 Subject: Added "abc -luts" option, Improved Xilinx logic mapping --- techlibs/xilinx/synth_xilinx.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index fbcc9601..6358a266 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -97,7 +97,7 @@ struct SynthXilinxPass : public Pass { log(" opt -fast\n"); log("\n"); log(" map_luts:\n"); - log(" abc -lut 5:8 [-dff]\n"); + log(" abc -luts 2:2,3,6:5,10,20 [-dff]\n"); log(" clean\n"); log("\n"); log(" map_cells:\n"); @@ -204,7 +204,7 @@ struct SynthXilinxPass : public Pass { if (check_label(active, run_from, run_to, "map_luts")) { - Pass::call(design, "abc -lut 6:8" + string(retime ? " -dff" : "")); + Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); Pass::call(design, "clean"); } -- cgit v1.2.3