From 1afe6589df136375c4322c9f10812e3b57f1200e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 24 Nov 2013 20:44:00 +0100 Subject: Renamed stdcells_sim.v to simcells.v and fixed blackbox.v --- techlibs/common/Makefile.inc | 14 +- techlibs/common/blackbox.sed | 4 +- techlibs/common/simcells.v | 327 ++++++++++++++++++++++++++++++++++++++++ techlibs/common/simlib.v | 16 +- techlibs/common/stdcells_sim.v | 332 ----------------------------------------- 5 files changed, 348 insertions(+), 345 deletions(-) create mode 100644 techlibs/common/simcells.v delete mode 100644 techlibs/common/stdcells_sim.v (limited to 'techlibs') diff --git a/techlibs/common/Makefile.inc b/techlibs/common/Makefile.inc index e81d34fb..e2e1ba25 100644 --- a/techlibs/common/Makefile.inc +++ b/techlibs/common/Makefile.inc @@ -1,13 +1,21 @@ EXTRA_TARGETS += techlibs/common/blackbox.v -techlibs/common/blackbox.v: techlibs/common/blackbox.sed techlibs/common/simlib.v techlibs/common/stdcells_sim.v - cat techlibs/common/simlib.v techlibs/common/stdcells_sim.v | sed -rf techlibs/common/blackbox.sed > techlibs/common/blackbox.v.new +techlibs/common/blackbox.v: techlibs/common/blackbox.sed techlibs/common/simlib.v techlibs/common/simcells.v + cat techlibs/common/simlib.v techlibs/common/simcells.v | sed -rf techlibs/common/blackbox.sed > techlibs/common/blackbox.v.new mv techlibs/common/blackbox.v.new techlibs/common/blackbox.v -EXTRA_TARGETS += share/simlib.v +EXTRA_TARGETS += share/simlib.v share/simcells.v share/blackbox.v share/simlib.v: techlibs/common/simlib.v mkdir -p share cp techlibs/common/simlib.v share/simlib.v +share/simcells.v: techlibs/common/simcells.v + mkdir -p share + cp techlibs/common/simcells.v share/simcells.v + +share/blackbox.v: techlibs/common/blackbox.v + mkdir -p share + cp techlibs/common/blackbox.v share/blackbox.v + diff --git a/techlibs/common/blackbox.sed b/techlibs/common/blackbox.sed index 4e9a3a7c..21693ecd 100644 --- a/techlibs/common/blackbox.sed +++ b/techlibs/common/blackbox.sed @@ -1,4 +1,4 @@ #!/bin/sed -r -/^(wire|assign|reg)/ d; -/^(genvar|always|initial)/,/^end/ d; +/^(wire|assign|reg|event)/ d; +/^(genvar|generate|always|initial)/,/^end/ d; s/ reg / /; diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v new file mode 100644 index 00000000..10a809db --- /dev/null +++ b/techlibs/common/simcells.v @@ -0,0 +1,327 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * --- + * + * The internal logic cell simulation library. + * + * This verilog library contains simple simulation models for the internal + * logic cells ($_INV_ , $_AND_ , ...) that are generated by the default technology + * mapper (see "stdcells.v" in this directory) and expected by the "abc" pass. + * + */ + +module \$_INV_ (A, Y); +input A; +output Y; +assign Y = ~A; +endmodule + +module \$_AND_ (A, B, Y); +input A, B; +output Y; +assign Y = A & B; +endmodule + +module \$_OR_ (A, B, Y); +input A, B; +output Y; +assign Y = A | B; +endmodule + +module \$_XOR_ (A, B, Y); +input A, B; +output Y; +assign Y = A ^ B; +endmodule + +module \$_MUX_ (A, B, S, Y); +input A, B, S; +output Y; +assign Y = S ? B : A; +endmodule + +module \$_SR_NN_ (S, R, Q); +input S, R; +output reg Q; +always @(negedge S, negedge R) begin + if (R == 0) + Q <= 0; + else if (S == 0) + Q <= 1; +end +endmodule + +module \$_SR_NP_ (S, R, Q); +input S, R; +output reg Q; +always @(negedge S, posedge R) begin + if (R == 1) + Q <= 0; + else if (S == 0) + Q <= 1; +end +endmodule + +module \$_SR_PN_ (S, R, Q); +input S, R; +output reg Q; +always @(posedge S, negedge R) begin + if (R == 0) + Q <= 0; + else if (S == 1) + Q <= 1; +end +endmodule + +module \$_SR_PP_ (S, R, Q); +input S, R; +output reg Q; +always @(posedge S, posedge R) begin + if (R == 1) + Q <= 0; + else if (S == 1) + Q <= 1; +end +endmodule + +module \$_DFF_N_ (D, Q, C); +input D, C; +output reg Q; +always @(negedge C) begin + Q <= D; +end +endmodule + +module \$_DFF_P_ (D, Q, C); +input D, C; +output reg Q; +always @(posedge C) begin + Q <= D; +end +endmodule + +module \$_DFF_NN0_ (D, Q, C, R); +input D, C, R; +output reg Q; +always @(negedge C or negedge R) begin + if (R == 0) + Q <= 0; + else + Q <= D; +end +endmodule + +module \$_DFF_NN1_ (D, Q, C, R); +input D, C, R; +output reg Q; +always @(negedge C or negedge R) begin + if (R == 0) + Q <= 1; + else + Q <= D; +end +endmodule + +module \$_DFF_NP0_ (D, Q, C, R); +input D, C, R; +output reg Q; +always @(negedge C or posedge R) begin + if (R == 1) + Q <= 0; + else + Q <= D; +end +endmodule + +module \$_DFF_NP1_ (D, Q, C, R); +input D, C, R; +output reg Q; +always @(negedge C or posedge R) begin + if (R == 1) + Q <= 1; + else + Q <= D; +end +endmodule + +module \$_DFF_PN0_ (D, Q, C, R); +input D, C, R; +output reg Q; +always @(posedge C or negedge R) begin + if (R == 0) + Q <= 0; + else + Q <= D; +end +endmodule + +module \$_DFF_PN1_ (D, Q, C, R); +input D, C, R; +output reg Q; +always @(posedge C or negedge R) begin + if (R == 0) + Q <= 1; + else + Q <= D; +end +endmodule + +module \$_DFF_PP0_ (D, Q, C, R); +input D, C, R; +output reg Q; +always @(posedge C or posedge R) begin + if (R == 1) + Q <= 0; + else + Q <= D; +end +endmodule + +module \$_DFF_PP1_ (D, Q, C, R); +input D, C, R; +output reg Q; +always @(posedge C or posedge R) begin + if (R == 1) + Q <= 1; + else + Q <= D; +end +endmodule + +module \$_DFFSR_NNN_ (C, S, R, D, Q); +input C, S, R, D; +output reg Q; +always @(negedge C, negedge S, negedge R) begin + if (R == 0) + Q <= 0; + else if (S == 0) + Q <= 1; + else + Q <= D; +end +endmodule + +module \$_DFFSR_NNP_ (C, S, R, D, Q); +input C, S, R, D; +output reg Q; +always @(negedge C, negedge S, posedge R) begin + if (R == 1) + Q <= 0; + else if (S == 0) + Q <= 1; + else + Q <= D; +end +endmodule + +module \$_DFFSR_NPN_ (C, S, R, D, Q); +input C, S, R, D; +output reg Q; +always @(negedge C, posedge S, negedge R) begin + if (R == 0) + Q <= 0; + else if (S == 1) + Q <= 1; + else + Q <= D; +end +endmodule + +module \$_DFFSR_NPP_ (C, S, R, D, Q); +input C, S, R, D; +output reg Q; +always @(negedge C, posedge S, posedge R) begin + if (R == 1) + Q <= 0; + else if (S == 1) + Q <= 1; + else + Q <= D; +end +endmodule + +module \$_DFFSR_PNN_ (C, S, R, D, Q); +input C, S, R, D; +output reg Q; +always @(posedge C, negedge S, negedge R) begin + if (R == 0) + Q <= 0; + else if (S == 0) + Q <= 1; + else + Q <= D; +end +endmodule + +module \$_DFFSR_PNP_ (C, S, R, D, Q); +input C, S, R, D; +output reg Q; +always @(posedge C, negedge S, posedge R) begin + if (R == 1) + Q <= 0; + else if (S == 0) + Q <= 1; + else + Q <= D; +end +endmodule + +module \$_DFFSR_PPN_ (C, S, R, D, Q); +input C, S, R, D; +output reg Q; +always @(posedge C, posedge S, negedge R) begin + if (R == 0) + Q <= 0; + else if (S == 1) + Q <= 1; + else + Q <= D; +end +endmodule + +module \$_DFFSR_PPP_ (C, S, R, D, Q); +input C, S, R, D; +output reg Q; +always @(posedge C, posedge S, posedge R) begin + if (R == 1) + Q <= 0; + else if (S == 1) + Q <= 1; + else + Q <= D; +end +endmodule + +module \$_DLATCH_N_ (E, D, Q); +input E, D; +output reg Q; +always @* begin + if (E == 0) + Q <= D; +end +endmodule + +module \$_DLATCH_P_ (E, D, Q); +input E, D; +output reg Q; +always @* begin + if (E == 1) + Q <= D; +end +endmodule + diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index beb2b885..b4440ea8 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -31,13 +31,11 @@ * */ -`define INPUT_A \ -input [A_WIDTH-1:0] A; \ -generate if (A_SIGNED) begin:A_BUF wire signed [A_WIDTH-1:0] val = A; end else begin:A_BUF wire [A_WIDTH-1:0] val = A; end endgenerate +`define INPUT_A input [A_WIDTH-1:0] A; \ + generate if (A_SIGNED) begin:A_BUF wire signed [A_WIDTH-1:0] val = A; end else begin:A_BUF wire [A_WIDTH-1:0] val = A; end endgenerate -`define INPUT_B \ -input [B_WIDTH-1:0] B; \ -generate if (B_SIGNED) begin:B_BUF wire signed [B_WIDTH-1:0] val = B; end else begin:B_BUF wire [B_WIDTH-1:0] val = B; end endgenerate +`define INPUT_B input [B_WIDTH-1:0] B; \ + generate if (B_SIGNED) begin:B_BUF wire signed [B_WIDTH-1:0] val = B; end else begin:B_BUF wire [B_WIDTH-1:0] val = B; end endgenerate // -------------------------------------------------------- @@ -661,7 +659,7 @@ generate end endgenerate -always @* +always @* begin casez ({I[WIDTH-1], lut0_out, lut1_out}) 3'b?11: O = 1'b1; 3'b?00: O = 1'b0; @@ -669,6 +667,7 @@ always @* 3'b1??: O = lut1_out; default: O = 1'bx; endcase +end endmodule @@ -784,9 +783,10 @@ input EN; input [WIDTH-1:0] D; output reg [WIDTH-1:0] Q; -always @* +always @* begin if (EN == EN_POLARITY) Q <= D; +end endmodule diff --git a/techlibs/common/stdcells_sim.v b/techlibs/common/stdcells_sim.v deleted file mode 100644 index 88284a09..00000000 --- a/techlibs/common/stdcells_sim.v +++ /dev/null @@ -1,332 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - * --- - * - * The internal logic cell simulation library. - * - * This verilog library contains simple simulation models for the internal - * logic cells ($_INV_ , $_AND_ , ...) that are generated by the default technology - * mapper (see "stdcells.v" in this directory) and expected by the "abc" pass. - * - */ - -module \$_INV_ (A, Y); -input A; -output Y; -assign Y = ~A; -endmodule - -module \$_AND_ (A, B, Y); -input A, B; -output Y; -assign Y = A & B; -endmodule - -module \$_OR_ (A, B, Y); -input A, B; -output Y; -assign Y = A | B; -endmodule - -module \$_XOR_ (A, B, Y); -input A, B; -output Y; -assign Y = A ^ B; -endmodule - -module \$_MUX_ (A, B, S, Y); -input A, B, S; -output reg Y; -always @* begin - if (S) - Y = B; - else - Y = A; -end -endmodule - -module \$_SR_NN_ (S, R, Q); -input S, R; -output reg Q; -always @(negedge S, negedge R) begin - if (R == 0) - Q <= 0; - else if (S == 0) - Q <= 1; -end -endmodule - -module \$_SR_NP_ (S, R, Q); -input S, R; -output reg Q; -always @(negedge S, posedge R) begin - if (R == 1) - Q <= 0; - else if (S == 0) - Q <= 1; -end -endmodule - -module \$_SR_PN_ (S, R, Q); -input S, R; -output reg Q; -always @(posedge S, negedge R) begin - if (R == 0) - Q <= 0; - else if (S == 1) - Q <= 1; -end -endmodule - -module \$_SR_PP_ (S, R, Q); -input S, R; -output reg Q; -always @(posedge S, posedge R) begin - if (R == 1) - Q <= 0; - else if (S == 1) - Q <= 1; -end -endmodule - -module \$_DFF_N_ (D, Q, C); -input D, C; -output reg Q; -always @(negedge C) begin - Q <= D; -end -endmodule - -module \$_DFF_P_ (D, Q, C); -input D, C; -output reg Q; -always @(posedge C) begin - Q <= D; -end -endmodule - -module \$_DFF_NN0_ (D, Q, C, R); -input D, C, R; -output reg Q; -always @(negedge C or negedge R) begin - if (R == 0) - Q <= 0; - else - Q <= D; -end -endmodule - -module \$_DFF_NN1_ (D, Q, C, R); -input D, C, R; -output reg Q; -always @(negedge C or negedge R) begin - if (R == 0) - Q <= 1; - else - Q <= D; -end -endmodule - -module \$_DFF_NP0_ (D, Q, C, R); -input D, C, R; -output reg Q; -always @(negedge C or posedge R) begin - if (R == 1) - Q <= 0; - else - Q <= D; -end -endmodule - -module \$_DFF_NP1_ (D, Q, C, R); -input D, C, R; -output reg Q; -always @(negedge C or posedge R) begin - if (R == 1) - Q <= 1; - else - Q <= D; -end -endmodule - -module \$_DFF_PN0_ (D, Q, C, R); -input D, C, R; -output reg Q; -always @(posedge C or negedge R) begin - if (R == 0) - Q <= 0; - else - Q <= D; -end -endmodule - -module \$_DFF_PN1_ (D, Q, C, R); -input D, C, R; -output reg Q; -always @(posedge C or negedge R) begin - if (R == 0) - Q <= 1; - else - Q <= D; -end -endmodule - -module \$_DFF_PP0_ (D, Q, C, R); -input D, C, R; -output reg Q; -always @(posedge C or posedge R) begin - if (R == 1) - Q <= 0; - else - Q <= D; -end -endmodule - -module \$_DFF_PP1_ (D, Q, C, R); -input D, C, R; -output reg Q; -always @(posedge C or posedge R) begin - if (R == 1) - Q <= 1; - else - Q <= D; -end -endmodule - -module \$_DFFSR_NNN_ (C, S, R, D, Q); -input C, S, R, D; -output reg Q; -always @(negedge C, negedge S, negedge R) begin - if (R == 0) - Q <= 0; - else if (S == 0) - Q <= 1; - else - Q <= D; -end -endmodule - -module \$_DFFSR_NNP_ (C, S, R, D, Q); -input C, S, R, D; -output reg Q; -always @(negedge C, negedge S, posedge R) begin - if (R == 1) - Q <= 0; - else if (S == 0) - Q <= 1; - else - Q <= D; -end -endmodule - -module \$_DFFSR_NPN_ (C, S, R, D, Q); -input C, S, R, D; -output reg Q; -always @(negedge C, posedge S, negedge R) begin - if (R == 0) - Q <= 0; - else if (S == 1) - Q <= 1; - else - Q <= D; -end -endmodule - -module \$_DFFSR_NPP_ (C, S, R, D, Q); -input C, S, R, D; -output reg Q; -always @(negedge C, posedge S, posedge R) begin - if (R == 1) - Q <= 0; - else if (S == 1) - Q <= 1; - else - Q <= D; -end -endmodule - -module \$_DFFSR_PNN_ (C, S, R, D, Q); -input C, S, R, D; -output reg Q; -always @(posedge C, negedge S, negedge R) begin - if (R == 0) - Q <= 0; - else if (S == 0) - Q <= 1; - else - Q <= D; -end -endmodule - -module \$_DFFSR_PNP_ (C, S, R, D, Q); -input C, S, R, D; -output reg Q; -always @(posedge C, negedge S, posedge R) begin - if (R == 1) - Q <= 0; - else if (S == 0) - Q <= 1; - else - Q <= D; -end -endmodule - -module \$_DFFSR_PPN_ (C, S, R, D, Q); -input C, S, R, D; -output reg Q; -always @(posedge C, posedge S, negedge R) begin - if (R == 0) - Q <= 0; - else if (S == 1) - Q <= 1; - else - Q <= D; -end -endmodule - -module \$_DFFSR_PPP_ (C, S, R, D, Q); -input C, S, R, D; -output reg Q; -always @(posedge C, posedge S, posedge R) begin - if (R == 1) - Q <= 0; - else if (S == 1) - Q <= 1; - else - Q <= D; -end -endmodule - -module \$_DLATCH_N_ (E, D, Q); -input E, D; -output reg Q; -always @* begin - if (E == 0) - Q <= D; -end -endmodule - -module \$_DLATCH_P_ (E, D, Q); -input E, D; -output reg Q; -always @* begin - if (E == 1) - Q <= D; -end -endmodule - -- cgit v1.2.3