From 4a9e133fabe85847f4cdaafed0b8024691be5395 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 18 Jan 2014 18:54:50 +0100 Subject: Fixed a type in $mem model in simlib.v --- techlibs/common/simlib.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index f3d652f0..321119e3 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1036,7 +1036,7 @@ generate end end end else - if (RD_CLK_POLARITY[i] == 1) begin:rd_posclk + if (WR_CLK_POLARITY[i] == 1) begin:rd_posclk always @(posedge WR_CLK[i]) if (WR_EN[i]) begin data[ WR_ADDR[ (i+1)*ABITS-1 : i*ABITS ] - OFFSET ] <= WR_DATA[ (i+1)*WIDTH-1 : i*WIDTH ]; -- cgit v1.2.3