From 9923762461d2bc0822daef76bf0b58e772045bc8 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 1 Sep 2014 15:37:56 +0200
Subject: Fixed "test_cell -simlib all"

---
 techlibs/common/simlib.v | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 09ffa9a6..3c931c81 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -108,12 +108,13 @@ parameter Y_WIDTH = 0;
 
 input [A_WIDTH-1:0] A;
 output [Y_WIDTH-1:0] Y;
+wire [Y_WIDTH-1:0] tmp;
 
 generate
 	if (A_SIGNED) begin:BLOCK1
-		assign Y = -$signed(A);
+		assign tmp = $signed(A), Y = -tmp;
 	end else begin:BLOCK2
-		assign Y = -A;
+		assign tmp = A, Y = -tmp;
 	end
 endgenerate
 
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