From ed8ad99960992a2895e0965be1b84a1fdd5e4b8b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 31 Jan 2014 11:21:29 +0100 Subject: More changes to techlibs/common/simlib.v for LEC --- techlibs/common/simlib.v | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) (limited to 'techlibs') diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 07bf43d0..c0c564fc 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1124,14 +1124,19 @@ task tr_fetch; endtask always @(posedge pos_clk, posedge pos_arst) begin - if (pos_arst) + if (pos_arst) begin state_tmp = STATE_TABLE[STATE_BITS*(STATE_RST+1)-1:STATE_BITS*STATE_RST]; - else + for (i = 0; i < STATE_BITS; i = i+1) + if (state_tmp[i] === 1'bz) + state_tmp[i] = 0; + state <= state_tmp; + end else begin state_tmp = next_state; - for (i = 0; i < STATE_BITS; i = i+1) - if (state_tmp[i] === 1'bz) - state_tmp[i] = 0; - state <= state_tmp; + for (i = 0; i < STATE_BITS; i = i+1) + if (state_tmp[i] === 1'bz) + state_tmp[i] = 0; + state <= state_tmp; + end end always @(state, CTRL_IN) begin -- cgit v1.2.3