From 482d9208aa9dacb7afe21f08c882d4881581013a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 12 Jun 2014 11:54:20 +0200 Subject: Added read_verilog -sv options, added support for bit, logic, allways_ff, always_comb, and always_latch --- tests/sat/asserts.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests/sat/asserts.ys') diff --git a/tests/sat/asserts.ys b/tests/sat/asserts.ys index de5e7c9a..d8f99492 100644 --- a/tests/sat/asserts.ys +++ b/tests/sat/asserts.ys @@ -1,3 +1,3 @@ -read_verilog asserts.v +read_verilog -sv asserts.v hierarchy; proc; opt sat -verify -seq 1 -set-at 1 rst 1 -tempinduct -prove-asserts -- cgit v1.2.3