From 5640b7d6078a681e33e85f06920394204f41c875 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 31 Mar 2013 11:17:56 +0200
Subject: Added test cases from 2012 paper on comparison of foss verilog
 synthesis tools

---
 tests/simple/forgen01.v | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)
 create mode 100644 tests/simple/forgen01.v

(limited to 'tests/simple/forgen01.v')

diff --git a/tests/simple/forgen01.v b/tests/simple/forgen01.v
new file mode 100644
index 00000000..70ee7e66
--- /dev/null
+++ b/tests/simple/forgen01.v
@@ -0,0 +1,20 @@
+module uut_forgen01(a, y);
+
+input [4:0] a;
+output y;
+
+integer i, j;
+reg [31:0] lut;
+
+initial begin
+	for (i = 0; i < 32; i = i+1) begin
+		lut[i] = i > 1;
+		for (j = 2; j*j <= i; j = j+1)
+			if (i % j == 0)
+				lut[i] = 0;
+	end
+end
+
+assign y = lut[a];
+
+endmodule
-- 
cgit v1.2.3