From 7764d0ba1dcf064ae487ee985c43083a0909e7f4 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 5 Jan 2013 11:13:26 +0100
Subject: initial import

---
 tests/simple/muxtree.v | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)
 create mode 100644 tests/simple/muxtree.v

(limited to 'tests/simple/muxtree.v')

diff --git a/tests/simple/muxtree.v b/tests/simple/muxtree.v
new file mode 100644
index 00000000..6996206c
--- /dev/null
+++ b/tests/simple/muxtree.v
@@ -0,0 +1,50 @@
+
+// test case generated from IWLS 2005 usb_phy core
+// (triggered a bug in opt_muxtree pass)
+
+module usb_tx_phy(clk, rst, DataOut_i, TxValid_i, hold_reg);
+
+input		clk;
+input		rst;
+input		DataOut_i;
+input		TxValid_i;
+output reg	hold_reg;
+
+reg		state, next_state;
+reg		ld_sop_d;
+reg		ld_data_d;
+
+always @(posedge clk)
+	if(ld_sop_d)
+		hold_reg <= 0;
+	else
+		hold_reg <= DataOut_i;
+
+always @(posedge clk)
+	if(!rst)	state <= 0;
+	else		state <= next_state;
+
+always @(state or TxValid_i)
+   begin
+	next_state = state;
+
+	ld_sop_d = 1'b0;
+	ld_data_d = 1'b0;
+
+	case(state)	// synopsys full_case parallel_case
+	   0:
+			if(TxValid_i)
+			   begin
+				ld_sop_d = 1'b1;
+				next_state = 1;
+			   end
+	   1:
+			if(TxValid_i)
+			   begin
+				ld_data_d = 1'b1;
+				next_state = 0;
+			   end
+	endcase
+   end
+
+endmodule
-- 
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