From 628b994cf6223a03d0d57bad193675dc93e88d65 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 24 Oct 2013 16:54:05 +0200
Subject: Added support for complex set-reset flip-flops in proc_dff

---
 tests/simple/dff_different_styles.v | 38 +++++++++++++++++++++++++------------
 1 file changed, 26 insertions(+), 12 deletions(-)

(limited to 'tests/simple')

diff --git a/tests/simple/dff_different_styles.v b/tests/simple/dff_different_styles.v
index db88b835..2f2737c4 100644
--- a/tests/simple/dff_different_styles.v
+++ b/tests/simple/dff_different_styles.v
@@ -65,6 +65,10 @@ always @(posedge clk, posedge arst1, posedge arst2, negedge arst3) begin
 end
 endmodule
 
+// SR-Flip-Flops are on the edge of well defined vewrilog constructs in terms of
+// simulation-implementation mismatches. The following testcases try to cover the
+// part that is defined and avoid the undefined cases.
+
 module dffsr1(clk, arst, d, q);
 input clk, arst, d;
 output reg q;
@@ -76,16 +80,26 @@ always @(posedge clk, posedge arst) begin
 end
 endmodule
 
-// module dffsr2(clk, preset, clear, d, q);
-// input clk, preset, clear, d;
-// output reg q;
-// always @(posedge clk, posedge preset, posedge clear) begin
-// 	if (preset)
-// 		q <= 1;
-// 	else if (clear)
-// 		q <= 0;
-// 	else
-// 		q <= d;
-// end
-// endmodule
+module dffsr2(clk, preset, clear, d, q);
+input clk, preset, clear, d;
+output q;
+(* gentb_clock *)
+wire clk, preset, clear, d;
+dffsr2_sub uut (clk, preset && !clear, !preset && clear, d, q);
+endmodule
+
+(* gentb_skip *)
+module dffsr2_sub(clk, preset, clear, d, q);
+input clk, preset, clear, d;
+output reg q;
+always @(posedge clk, posedge preset, posedge clear) begin
+	if (preset)
+		q <= 1;
+	else if (clear)
+		q <= 0;
+	else
+		q <= d;
+end
+endmodule
+
 
-- 
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