From 9b183539af4adf7d2a127042ca384806c7e73367 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 17 Jul 2014 16:49:23 +0200 Subject: Implemented dynamic bit-/part-select for memory writes --- tests/simple/memory.v | 41 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) (limited to 'tests/simple') diff --git a/tests/simple/memory.v b/tests/simple/memory.v index 21271b5e..ae63e8a1 100644 --- a/tests/simple/memory.v +++ b/tests/simple/memory.v @@ -137,7 +137,26 @@ endmodule // ---------------------------------------------------------- -module test06(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:0] dout); +module test06_sync(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:0] dout); + (* gentb_constant=0 *) wire rst; + reg [7:0] test [0:7]; + integer i; + always @(posedge clk) begin + if (rst) begin + for (i=0; i<8; i=i+1) + test[i] <= 0; + end else begin + test[0][2] <= din[1]; + test[0][5] <= test[0][2]; + test[idx][3] <= din[idx]; + test[idx][6] <= test[idx][2]; + test[idx][idx] <= !test[idx][idx]; + end + end + assign dout = test[idx]; +endmodule + +module test06_async(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:0] dout); (* gentb_constant=0 *) wire rst; reg [7:0] test [0:7]; integer i; @@ -155,3 +174,23 @@ module test06(input clk, input rst, input [2:0] idx, input [7:0] din, output [7: end assign dout = test[idx]; endmodule + +// ---------------------------------------------------------- + +module test07(clk, addr, woffset, wdata, rdata); + +input clk; +input [1:0] addr; +input [3:0] wdata; +input [1:0] woffset; +output reg [7:0] rdata; + +reg [7:0] mem [0:3]; + +integer i; +always @(posedge clk) begin + mem[addr][woffset +: 4] <= wdata; + rdata <= mem[addr]; +end + +endmodule -- cgit v1.2.3