From a6750b375301f2c2ebb51a2496cdf2c820b2546b Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 3 Feb 2014 13:01:45 +0100
Subject: Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)

---
 tests/simple/memory.v | 39 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

(limited to 'tests/simple')

diff --git a/tests/simple/memory.v b/tests/simple/memory.v
index eaeee01d..927ee043 100644
--- a/tests/simple/memory.v
+++ b/tests/simple/memory.v
@@ -75,3 +75,42 @@ assign y4 = mem2[addr][bit];
 
 endmodule
 
+// ----------------------------------------------------------
+
+module test03(clk, wr_addr, wr_data, wr_enable, rd_addr, rd_data);
+
+input clk, wr_enable;
+input [3:0] wr_addr, wr_data, rd_addr;
+output reg [3:0] rd_data;
+
+reg [3:0] memory [0:15];
+
+always @(posedge clk) begin
+	if (wr_enable)
+		memory[wr_addr] <= wr_data;
+	rd_data <= memory[rd_addr];
+end
+
+endmodule
+
+// ----------------------------------------------------------
+
+module test04(clk, wr_addr, wr_data, wr_enable, rd_addr, rd_data);
+
+input clk, wr_enable;
+input [3:0] wr_addr, wr_data, rd_addr;
+output [3:0] rd_data;
+
+reg rd_addr_buf;
+reg [3:0] memory [0:15];
+
+always @(posedge clk) begin
+	if (wr_enable)
+		memory[wr_addr] <= wr_data;
+	rd_addr_buf <= rd_addr;
+end
+
+assign rd_data = memory[rd_addr_buf];
+
+endmodule
+
-- 
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