From a67cd2d4a284cb945af6d477cc215cef7bdd22a8 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 17 Mar 2014 01:56:00 +0100
Subject: Progress in Verific bindings

---
 tests/simple/forgen01.v | 3 +++
 tests/simple/mem_arst.v | 2 +-
 2 files changed, 4 insertions(+), 1 deletion(-)

(limited to 'tests/simple')

diff --git a/tests/simple/forgen01.v b/tests/simple/forgen01.v
index 70ee7e66..8b7aa279 100644
--- a/tests/simple/forgen01.v
+++ b/tests/simple/forgen01.v
@@ -1,3 +1,6 @@
+
+// VERIFIC-SKIP
+
 module uut_forgen01(a, y);
 
 input [4:0] a;
diff --git a/tests/simple/mem_arst.v b/tests/simple/mem_arst.v
index 4022f57c..9bd38fcb 100644
--- a/tests/simple/mem_arst.v
+++ b/tests/simple/mem_arst.v
@@ -10,7 +10,7 @@ module MyMem #(
   output [DataWidth-1:0] Data_o,
   input                  WR_i);
 
-  reg Data_o;
+  reg [DataWidth-1:0] Data_o;
 
   localparam Size = 2**AddrWidth;
 
-- 
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