From 56432a920f9c2189ead2f724f18cde20aad7bf99 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 4 Jul 2013 14:12:33 +0200 Subject: Added defparam support to Verilog/AST frontend --- tests/simple/paramods.v | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'tests') diff --git a/tests/simple/paramods.v b/tests/simple/paramods.v index 94fd2dfc..8d0134a6 100644 --- a/tests/simple/paramods.v +++ b/tests/simple/paramods.v @@ -23,6 +23,22 @@ endmodule // ----------------------------------- +module test3(a, b, x, y); + +input [7:0] a, b; +output [7:0] x, y; + +inc inc_a (.in(a), .out(x)); +inc inc_b (b, y); + +defparam inc_a.step = 3; +defparam inc_b.step = 7; +defparam inc_b.width = 4; + +endmodule + +// ----------------------------------- + module inc(in, out); parameter width = 8; -- cgit v1.2.3