From 5dab327b30cb1d864297b22a15f0fce4b374a841 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 9 Jul 2013 23:41:28 +0200 Subject: More fixes in ast expression sign/width handling --- tests/simple/vloghammer.v | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) (limited to 'tests') diff --git a/tests/simple/vloghammer.v b/tests/simple/vloghammer.v index 9269ff05..09987e7c 100644 --- a/tests/simple/vloghammer.v +++ b/tests/simple/vloghammer.v @@ -27,19 +27,21 @@ module test04(a, y); assign y = ~(a - 1'b0); endmodule -module test05(a, y); - input a; - output y; - assign y = 12345 >> {a, 32'd0}; -endmodule - -module test06(a, b, c, y); - input signed [3:0] a; - input signed [1:0] b; - input signed [1:0] c; - output [5:0] y; - assign y = (a >> b) >>> c; -endmodule +// .. this test triggers a bug in xilinx isim. +// module test05(a, y); +// input a; +// output y; +// assign y = 12345 >> {a, 32'd0}; +// endmodule + +// .. this test triggers a bug in icarus verilog. +// module test06(a, b, c, y); +// input signed [3:0] a; +// input signed [1:0] b; +// input signed [1:0] c; +// output [5:0] y; +// assign y = (a >> b) >>> c; +// endmodule module test07(a, b, y); input signed [1:0] a; -- cgit v1.2.3