From 5e641acc905a5c99d037378f6b7a481c43eb7de0 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 1 Aug 2014 03:57:37 +0200
Subject: Consolidated hana test benches into fewer files

for pf in test_simulation_{always,and,buffer,decoder,inc,mux,nand,nor,or,seq,shifter,sop,techmap,xnor,xor}; do
gawk 'FNR == 1 { printf("\n// %s\n",FILENAME); } { gsub("^module *", sprintf("module f%d_",ARGIND)); print; }' \
    ${pf}_*_test.v > $pf.v; ../tools/autotest.sh $pf.v; mv -v ${pf}_*_test.v Attic/; done;

..etc..
---
 tests/hana/README                                  |  10 -
 tests/hana/run-test.sh                             |   2 +-
 tests/hana/test_intermout.v                        | 418 +++++++++++++++++++++
 tests/hana/test_intermout_always_comb_1_test.v     |  13 -
 tests/hana/test_intermout_always_comb_3_test.v     |  10 -
 tests/hana/test_intermout_always_comb_4_test.v     |   9 -
 tests/hana/test_intermout_always_comb_5_test.v     |  11 -
 tests/hana/test_intermout_always_ff_3_test.v       |  15 -
 tests/hana/test_intermout_always_ff_4_test.v       |  11 -
 tests/hana/test_intermout_always_ff_5_test.v       |  13 -
 tests/hana/test_intermout_always_ff_6_test.v       |   7 -
 tests/hana/test_intermout_always_ff_8_test.v       |  11 -
 tests/hana/test_intermout_always_ff_9_test.v       |  14 -
 tests/hana/test_intermout_always_latch_1_test.v    |   9 -
 tests/hana/test_intermout_bufrm_1_test.v           |   4 -
 tests/hana/test_intermout_bufrm_2_test.v           |   7 -
 tests/hana/test_intermout_bufrm_6_test.v           |  22 --
 tests/hana/test_intermout_bufrm_7_test.v           |  33 --
 tests/hana/test_intermout_exprs_add_test.v         |  10 -
 tests/hana/test_intermout_exprs_binlogic_test.v    |  13 -
 tests/hana/test_intermout_exprs_bitwiseneg_test.v  |   5 -
 tests/hana/test_intermout_exprs_buffer_test.v      |   9 -
 .../hana/test_intermout_exprs_condexpr_mux_test.v  |  11 -
 .../test_intermout_exprs_condexpr_tribuf_test.v    |   9 -
 tests/hana/test_intermout_exprs_const_test.v       |   7 -
 tests/hana/test_intermout_exprs_constshift_test.v  |  12 -
 tests/hana/test_intermout_exprs_div_test.v         |  10 -
 tests/hana/test_intermout_exprs_logicneg_test.v    |   7 -
 tests/hana/test_intermout_exprs_mod_test.v         |  10 -
 tests/hana/test_intermout_exprs_mul_test.v         |  10 -
 tests/hana/test_intermout_exprs_redand_test.v      |   5 -
 tests/hana/test_intermout_exprs_redop_test.v       |  16 -
 tests/hana/test_intermout_exprs_sub_test.v         |  10 -
 tests/hana/test_intermout_exprs_unaryminus_test.v  |   5 -
 tests/hana/test_intermout_exprs_unaryplus_test.v   |   4 -
 tests/hana/test_intermout_exprs_varshift_test.v    |  10 -
 tests/hana/test_parse2synthtrans.v                 | 117 ++++++
 tests/hana/test_parse2synthtrans_behavopt_1_test.v |  22 --
 tests/hana/test_parse2synthtrans_case_1_test.v     |  26 --
 .../hana/test_parse2synthtrans_contassign_1_test.v |   7 -
 .../test_parse2synthtrans_module_basic0_test.v     |   2 -
 .../hana/test_parse2synthtrans_operators_1_test.v  |  11 -
 tests/hana/test_parse2synthtrans_param_1_test.v    |   7 -
 .../test_parse2synthtrans_port_scalar_1_test.v     |   6 -
 .../test_parse2synthtrans_port_vector_1_test.v     |   9 -
 ...arse2synthtrans_v2k_comb_logic_sens_list_test.v |   9 -
 tests/hana/test_parser.v                           |  87 +++++
 .../test_parser_constructs_module_basic1_test.v    |   2 -
 .../test_parser_constructs_param_basic0_test.v     |  10 -
 .../hana/test_parser_constructs_port_basic0_test.v |   8 -
 .../test_parser_directives_define_simpledef_test.v |   9 -
 tests/hana/test_parser_misc_operators_test.v       |  29 --
 .../test_parser_v2k_comb_port_data_type_test.v     |   6 -
 .../test_parser_v2k_comma_sep_sens_list_test.v     |   9 -
 tests/hana/test_simulation_always.v                | 135 +++++++
 tests/hana/test_simulation_always_15_test.v        |   5 -
 tests/hana/test_simulation_always_17_test.v        |  13 -
 tests/hana/test_simulation_always_18_test.v        |  10 -
 tests/hana/test_simulation_always_19_test.v        |  11 -
 tests/hana/test_simulation_always_1_test.v         |   5 -
 tests/hana/test_simulation_always_20_test.v        |  15 -
 tests/hana/test_simulation_always_21_test.v        |  11 -
 tests/hana/test_simulation_always_22_test.v        |   7 -
 tests/hana/test_simulation_always_23_test.v        |  14 -
 tests/hana/test_simulation_always_27_test.v        |  13 -
 tests/hana/test_simulation_always_29_test.v        |   9 -
 tests/hana/test_simulation_always_31_tt.v          |  50 ---
 tests/hana/test_simulation_and.v                   |  35 ++
 tests/hana/test_simulation_and_1_test.v            |   3 -
 tests/hana/test_simulation_and_2_test.v            |   3 -
 tests/hana/test_simulation_and_3_test.v            |   3 -
 tests/hana/test_simulation_and_4_test.v            |   3 -
 tests/hana/test_simulation_and_5_test.v            |   3 -
 tests/hana/test_simulation_and_6_test.v            |   3 -
 tests/hana/test_simulation_and_7_test.v            |   3 -
 tests/hana/test_simulation_buffer.v                |  17 +
 tests/hana/test_simulation_buffer_1_test.v         |   3 -
 tests/hana/test_simulation_buffer_2_test.v         |   4 -
 tests/hana/test_simulation_buffer_3_test.v         |   4 -
 tests/hana/test_simulation_decoder.v               | 219 +++++++++++
 tests/hana/test_simulation_decoder_2_test.v        |  14 -
 tests/hana/test_simulation_decoder_3_test.v        |  14 -
 tests/hana/test_simulation_decoder_4_test.v        |  14 -
 tests/hana/test_simulation_decoder_5_test.v        |  17 -
 tests/hana/test_simulation_decoder_6_test.v        |  27 --
 tests/hana/test_simulation_decoder_7_test.v        |  43 ---
 tests/hana/test_simulation_decoder_8_test.v        |  76 ----
 tests/hana/test_simulation_inc.v                   |  42 +++
 tests/hana/test_simulation_inc_16_test.v           |   5 -
 tests/hana/test_simulation_inc_1_test.v            |   5 -
 tests/hana/test_simulation_inc_2_test.v            |   5 -
 tests/hana/test_simulation_inc_32_test.v           |   5 -
 tests/hana/test_simulation_inc_4_test.v            |   5 -
 tests/hana/test_simulation_inc_8_test.v            |   5 -
 tests/hana/test_simulation_mod_1_xx.v              |  13 -
 tests/hana/test_simulation_mux.v                   | 176 +++++++++
 tests/hana/test_simulation_mux_16_test.v           |  22 --
 tests/hana/test_simulation_mux_2_test.v            |   8 -
 tests/hana/test_simulation_mux_32_test.v           |  39 --
 tests/hana/test_simulation_mux_4_test.v            |  10 -
 tests/hana/test_simulation_mux_64_test.v           |  71 ----
 tests/hana/test_simulation_mux_8_test.v            |  14 -
 tests/hana/test_simulation_nand.v                  |  25 ++
 tests/hana/test_simulation_nand_1_test.v           |   3 -
 tests/hana/test_simulation_nand_3_test.v           |   3 -
 tests/hana/test_simulation_nand_4_test.v           |   3 -
 tests/hana/test_simulation_nand_5_test.v           |   3 -
 tests/hana/test_simulation_nand_6_test.v           |   3 -
 tests/hana/test_simulation_nor.v                   |  20 +
 tests/hana/test_simulation_nor_1_test.v            |   3 -
 tests/hana/test_simulation_nor_2_test.v            |   3 -
 tests/hana/test_simulation_nor_3_test.v            |   3 -
 tests/hana/test_simulation_nor_4_test.v            |   3 -
 ...st_simulation_opt_constprop_contassign_1_test.v |   3 -
 tests/hana/test_simulation_or.v                    |  30 ++
 tests/hana/test_simulation_or_1_test.v             |   3 -
 tests/hana/test_simulation_or_2_test.v             |   3 -
 tests/hana/test_simulation_or_3_test.v             |   3 -
 tests/hana/test_simulation_or_4_test.v             |   3 -
 tests/hana/test_simulation_or_5_test.v             |   3 -
 tests/hana/test_simulation_or_6_test.v             |   3 -
 tests/hana/test_simulation_seq.v                   |  12 +
 tests/hana/test_simulation_seq_ff_1_test.v         |   4 -
 tests/hana/test_simulation_seq_ff_2_test.v         |   4 -
 tests/hana/test_simulation_shifter.v               |  60 +++
 tests/hana/test_simulation_shifter_left_16_test.v  |   4 -
 tests/hana/test_simulation_shifter_left_32_test.v  |   4 -
 tests/hana/test_simulation_shifter_left_4_test.v   |   4 -
 tests/hana/test_simulation_shifter_left_64_test.v  |   4 -
 tests/hana/test_simulation_shifter_left_8_test.v   |   4 -
 tests/hana/test_simulation_shifter_right_16_test.v |   4 -
 tests/hana/test_simulation_shifter_right_32_test.v |   4 -
 tests/hana/test_simulation_shifter_right_4_test.v  |   4 -
 tests/hana/test_simulation_shifter_right_64_test.v |   4 -
 tests/hana/test_simulation_shifter_right_8_test.v  |   4 -
 tests/hana/test_simulation_sop.v                   |  65 ++++
 tests/hana/test_simulation_sop_basic_10_test.v     |   8 -
 tests/hana/test_simulation_sop_basic_11_test.v     |  10 -
 tests/hana/test_simulation_sop_basic_12_test.v     |  14 -
 tests/hana/test_simulation_sop_basic_18_test.v     |   5 -
 tests/hana/test_simulation_sop_basic_3_test.v      |   3 -
 tests/hana/test_simulation_sop_basic_7_test.v      |   3 -
 tests/hana/test_simulation_sop_basic_8_test.v      |   3 -
 tests/hana/test_simulation_sop_basic_9_test.v      |   3 -
 tests/hana/test_simulation_techmap.v               | 172 +++++++++
 tests/hana/test_simulation_techmap_and_19_tech.v   |   7 -
 tests/hana/test_simulation_techmap_and_5_tech.v    |   3 -
 tests/hana/test_simulation_techmap_buf_test.v      |   3 -
 tests/hana/test_simulation_techmap_inv_test.v      |   3 -
 tests/hana/test_simulation_techmap_mux_0_test.v    |   8 -
 tests/hana/test_simulation_techmap_mux_128_test.v  | 134 -------
 tests/hana/test_simulation_techmap_mux_8_test.v    |  14 -
 tests/hana/test_simulation_techmap_nand_19_tech.v  |  11 -
 tests/hana/test_simulation_techmap_nand_2_tech.v   |  11 -
 tests/hana/test_simulation_techmap_nand_5_tech.v   |  11 -
 tests/hana/test_simulation_techmap_nor_19_tech.v   |  11 -
 tests/hana/test_simulation_techmap_nor_2_tech.v    |  11 -
 tests/hana/test_simulation_techmap_nor_5_tech.v    |  11 -
 tests/hana/test_simulation_techmap_or_19_tech.v    |   7 -
 tests/hana/test_simulation_techmap_or_5_tech.v     |   3 -
 tests/hana/test_simulation_techmap_tech.v          | 143 +++++++
 tests/hana/test_simulation_techmap_xnor_2_tech.v   |   6 -
 tests/hana/test_simulation_techmap_xnor_5_tech.v   |   6 -
 tests/hana/test_simulation_techmap_xor_19_tech.v   |   3 -
 tests/hana/test_simulation_techmap_xor_2_tech.v    |   6 -
 tests/hana/test_simulation_techmap_xor_5_tech.v    |   6 -
 tests/hana/test_simulation_tribuf_2_test.v         |   3 -
 tests/hana/test_simulation_vlib.v                  |  65 ++++
 tests/hana/test_simulation_xnor.v                  |  20 +
 tests/hana/test_simulation_xnor_1_test.v           |   3 -
 tests/hana/test_simulation_xnor_2_test.v           |   3 -
 tests/hana/test_simulation_xnor_3_test.v           |   3 -
 tests/hana/test_simulation_xnor_4_test.v           |   3 -
 tests/hana/test_simulation_xor.v                   |  20 +
 tests/hana/test_simulation_xor_1_test.v            |   3 -
 tests/hana/test_simulation_xor_2_test.v            |   3 -
 tests/hana/test_simulation_xor_3_test.v            |   3 -
 tests/hana/test_simulation_xor_4_test.v            |   3 -
 178 files changed, 1879 insertions(+), 1589 deletions(-)
 create mode 100644 tests/hana/test_intermout.v
 delete mode 100644 tests/hana/test_intermout_always_comb_1_test.v
 delete mode 100644 tests/hana/test_intermout_always_comb_3_test.v
 delete mode 100644 tests/hana/test_intermout_always_comb_4_test.v
 delete mode 100644 tests/hana/test_intermout_always_comb_5_test.v
 delete mode 100644 tests/hana/test_intermout_always_ff_3_test.v
 delete mode 100644 tests/hana/test_intermout_always_ff_4_test.v
 delete mode 100644 tests/hana/test_intermout_always_ff_5_test.v
 delete mode 100644 tests/hana/test_intermout_always_ff_6_test.v
 delete mode 100644 tests/hana/test_intermout_always_ff_8_test.v
 delete mode 100644 tests/hana/test_intermout_always_ff_9_test.v
 delete mode 100644 tests/hana/test_intermout_always_latch_1_test.v
 delete mode 100644 tests/hana/test_intermout_bufrm_1_test.v
 delete mode 100644 tests/hana/test_intermout_bufrm_2_test.v
 delete mode 100644 tests/hana/test_intermout_bufrm_6_test.v
 delete mode 100644 tests/hana/test_intermout_bufrm_7_test.v
 delete mode 100644 tests/hana/test_intermout_exprs_add_test.v
 delete mode 100644 tests/hana/test_intermout_exprs_binlogic_test.v
 delete mode 100644 tests/hana/test_intermout_exprs_bitwiseneg_test.v
 delete mode 100644 tests/hana/test_intermout_exprs_buffer_test.v
 delete mode 100644 tests/hana/test_intermout_exprs_condexpr_mux_test.v
 delete mode 100644 tests/hana/test_intermout_exprs_condexpr_tribuf_test.v
 delete mode 100644 tests/hana/test_intermout_exprs_const_test.v
 delete mode 100644 tests/hana/test_intermout_exprs_constshift_test.v
 delete mode 100644 tests/hana/test_intermout_exprs_div_test.v
 delete mode 100644 tests/hana/test_intermout_exprs_logicneg_test.v
 delete mode 100644 tests/hana/test_intermout_exprs_mod_test.v
 delete mode 100644 tests/hana/test_intermout_exprs_mul_test.v
 delete mode 100644 tests/hana/test_intermout_exprs_redand_test.v
 delete mode 100644 tests/hana/test_intermout_exprs_redop_test.v
 delete mode 100644 tests/hana/test_intermout_exprs_sub_test.v
 delete mode 100644 tests/hana/test_intermout_exprs_unaryminus_test.v
 delete mode 100644 tests/hana/test_intermout_exprs_unaryplus_test.v
 delete mode 100644 tests/hana/test_intermout_exprs_varshift_test.v
 create mode 100644 tests/hana/test_parse2synthtrans.v
 delete mode 100644 tests/hana/test_parse2synthtrans_behavopt_1_test.v
 delete mode 100644 tests/hana/test_parse2synthtrans_case_1_test.v
 delete mode 100644 tests/hana/test_parse2synthtrans_contassign_1_test.v
 delete mode 100644 tests/hana/test_parse2synthtrans_module_basic0_test.v
 delete mode 100644 tests/hana/test_parse2synthtrans_operators_1_test.v
 delete mode 100644 tests/hana/test_parse2synthtrans_param_1_test.v
 delete mode 100644 tests/hana/test_parse2synthtrans_port_scalar_1_test.v
 delete mode 100644 tests/hana/test_parse2synthtrans_port_vector_1_test.v
 delete mode 100644 tests/hana/test_parse2synthtrans_v2k_comb_logic_sens_list_test.v
 create mode 100644 tests/hana/test_parser.v
 delete mode 100644 tests/hana/test_parser_constructs_module_basic1_test.v
 delete mode 100644 tests/hana/test_parser_constructs_param_basic0_test.v
 delete mode 100644 tests/hana/test_parser_constructs_port_basic0_test.v
 delete mode 100644 tests/hana/test_parser_directives_define_simpledef_test.v
 delete mode 100644 tests/hana/test_parser_misc_operators_test.v
 delete mode 100644 tests/hana/test_parser_v2k_comb_port_data_type_test.v
 delete mode 100644 tests/hana/test_parser_v2k_comma_sep_sens_list_test.v
 create mode 100644 tests/hana/test_simulation_always.v
 delete mode 100644 tests/hana/test_simulation_always_15_test.v
 delete mode 100644 tests/hana/test_simulation_always_17_test.v
 delete mode 100644 tests/hana/test_simulation_always_18_test.v
 delete mode 100644 tests/hana/test_simulation_always_19_test.v
 delete mode 100644 tests/hana/test_simulation_always_1_test.v
 delete mode 100644 tests/hana/test_simulation_always_20_test.v
 delete mode 100644 tests/hana/test_simulation_always_21_test.v
 delete mode 100644 tests/hana/test_simulation_always_22_test.v
 delete mode 100644 tests/hana/test_simulation_always_23_test.v
 delete mode 100644 tests/hana/test_simulation_always_27_test.v
 delete mode 100644 tests/hana/test_simulation_always_29_test.v
 delete mode 100644 tests/hana/test_simulation_always_31_tt.v
 create mode 100644 tests/hana/test_simulation_and.v
 delete mode 100644 tests/hana/test_simulation_and_1_test.v
 delete mode 100644 tests/hana/test_simulation_and_2_test.v
 delete mode 100644 tests/hana/test_simulation_and_3_test.v
 delete mode 100644 tests/hana/test_simulation_and_4_test.v
 delete mode 100644 tests/hana/test_simulation_and_5_test.v
 delete mode 100644 tests/hana/test_simulation_and_6_test.v
 delete mode 100644 tests/hana/test_simulation_and_7_test.v
 create mode 100644 tests/hana/test_simulation_buffer.v
 delete mode 100644 tests/hana/test_simulation_buffer_1_test.v
 delete mode 100644 tests/hana/test_simulation_buffer_2_test.v
 delete mode 100644 tests/hana/test_simulation_buffer_3_test.v
 create mode 100644 tests/hana/test_simulation_decoder.v
 delete mode 100644 tests/hana/test_simulation_decoder_2_test.v
 delete mode 100644 tests/hana/test_simulation_decoder_3_test.v
 delete mode 100644 tests/hana/test_simulation_decoder_4_test.v
 delete mode 100644 tests/hana/test_simulation_decoder_5_test.v
 delete mode 100644 tests/hana/test_simulation_decoder_6_test.v
 delete mode 100644 tests/hana/test_simulation_decoder_7_test.v
 delete mode 100644 tests/hana/test_simulation_decoder_8_test.v
 create mode 100644 tests/hana/test_simulation_inc.v
 delete mode 100644 tests/hana/test_simulation_inc_16_test.v
 delete mode 100644 tests/hana/test_simulation_inc_1_test.v
 delete mode 100644 tests/hana/test_simulation_inc_2_test.v
 delete mode 100644 tests/hana/test_simulation_inc_32_test.v
 delete mode 100644 tests/hana/test_simulation_inc_4_test.v
 delete mode 100644 tests/hana/test_simulation_inc_8_test.v
 delete mode 100644 tests/hana/test_simulation_mod_1_xx.v
 create mode 100644 tests/hana/test_simulation_mux.v
 delete mode 100644 tests/hana/test_simulation_mux_16_test.v
 delete mode 100644 tests/hana/test_simulation_mux_2_test.v
 delete mode 100644 tests/hana/test_simulation_mux_32_test.v
 delete mode 100644 tests/hana/test_simulation_mux_4_test.v
 delete mode 100644 tests/hana/test_simulation_mux_64_test.v
 delete mode 100644 tests/hana/test_simulation_mux_8_test.v
 create mode 100644 tests/hana/test_simulation_nand.v
 delete mode 100644 tests/hana/test_simulation_nand_1_test.v
 delete mode 100644 tests/hana/test_simulation_nand_3_test.v
 delete mode 100644 tests/hana/test_simulation_nand_4_test.v
 delete mode 100644 tests/hana/test_simulation_nand_5_test.v
 delete mode 100644 tests/hana/test_simulation_nand_6_test.v
 create mode 100644 tests/hana/test_simulation_nor.v
 delete mode 100644 tests/hana/test_simulation_nor_1_test.v
 delete mode 100644 tests/hana/test_simulation_nor_2_test.v
 delete mode 100644 tests/hana/test_simulation_nor_3_test.v
 delete mode 100644 tests/hana/test_simulation_nor_4_test.v
 delete mode 100644 tests/hana/test_simulation_opt_constprop_contassign_1_test.v
 create mode 100644 tests/hana/test_simulation_or.v
 delete mode 100644 tests/hana/test_simulation_or_1_test.v
 delete mode 100644 tests/hana/test_simulation_or_2_test.v
 delete mode 100644 tests/hana/test_simulation_or_3_test.v
 delete mode 100644 tests/hana/test_simulation_or_4_test.v
 delete mode 100644 tests/hana/test_simulation_or_5_test.v
 delete mode 100644 tests/hana/test_simulation_or_6_test.v
 create mode 100644 tests/hana/test_simulation_seq.v
 delete mode 100644 tests/hana/test_simulation_seq_ff_1_test.v
 delete mode 100644 tests/hana/test_simulation_seq_ff_2_test.v
 create mode 100644 tests/hana/test_simulation_shifter.v
 delete mode 100644 tests/hana/test_simulation_shifter_left_16_test.v
 delete mode 100644 tests/hana/test_simulation_shifter_left_32_test.v
 delete mode 100644 tests/hana/test_simulation_shifter_left_4_test.v
 delete mode 100644 tests/hana/test_simulation_shifter_left_64_test.v
 delete mode 100644 tests/hana/test_simulation_shifter_left_8_test.v
 delete mode 100644 tests/hana/test_simulation_shifter_right_16_test.v
 delete mode 100644 tests/hana/test_simulation_shifter_right_32_test.v
 delete mode 100644 tests/hana/test_simulation_shifter_right_4_test.v
 delete mode 100644 tests/hana/test_simulation_shifter_right_64_test.v
 delete mode 100644 tests/hana/test_simulation_shifter_right_8_test.v
 create mode 100644 tests/hana/test_simulation_sop.v
 delete mode 100644 tests/hana/test_simulation_sop_basic_10_test.v
 delete mode 100644 tests/hana/test_simulation_sop_basic_11_test.v
 delete mode 100644 tests/hana/test_simulation_sop_basic_12_test.v
 delete mode 100644 tests/hana/test_simulation_sop_basic_18_test.v
 delete mode 100644 tests/hana/test_simulation_sop_basic_3_test.v
 delete mode 100644 tests/hana/test_simulation_sop_basic_7_test.v
 delete mode 100644 tests/hana/test_simulation_sop_basic_8_test.v
 delete mode 100644 tests/hana/test_simulation_sop_basic_9_test.v
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 delete mode 100644 tests/hana/test_simulation_techmap_mux_128_test.v
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 create mode 100644 tests/hana/test_simulation_techmap_tech.v
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 delete mode 100644 tests/hana/test_simulation_tribuf_2_test.v
 create mode 100644 tests/hana/test_simulation_vlib.v
 create mode 100644 tests/hana/test_simulation_xnor.v
 delete mode 100644 tests/hana/test_simulation_xnor_1_test.v
 delete mode 100644 tests/hana/test_simulation_xnor_2_test.v
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 delete mode 100644 tests/hana/test_simulation_xnor_4_test.v
 create mode 100644 tests/hana/test_simulation_xor.v
 delete mode 100644 tests/hana/test_simulation_xor_1_test.v
 delete mode 100644 tests/hana/test_simulation_xor_2_test.v
 delete mode 100644 tests/hana/test_simulation_xor_3_test.v
 delete mode 100644 tests/hana/test_simulation_xor_4_test.v

(limited to 'tests')

diff --git a/tests/hana/README b/tests/hana/README
index 37049405..b2a08fd4 100644
--- a/tests/hana/README
+++ b/tests/hana/README
@@ -2,13 +2,3 @@
 This test cases are copied from the hana project:
 https://sourceforge.net/projects/sim-sim/
 
-** Copy tests from hana: **
-while read fn; do cp -v $fn ALL_TESTS/${fn//\//_}; done < <(find test -name '*.v' ! -name '*_gold.v')
-
-** Eliminate test's we can't parse atm: **
-rm -f test_synthesizability*.v
-rm -f test_parse2synthtrans_latch_1_test.v
-rm -f test_parse2synthtrans_always_1_test.v
-rm -f test_parse2synthtrans_always_2_test.v
-for x in test_*.v; do ../../yosys -b "" $x || rm $x; done
-
diff --git a/tests/hana/run-test.sh b/tests/hana/run-test.sh
index 410f9b4d..d719c46b 100755
--- a/tests/hana/run-test.sh
+++ b/tests/hana/run-test.sh
@@ -1,2 +1,2 @@
 #!/bin/bash
-exec ${MAKE:-make} -f ../tools/autotest.mk EXTRA_FLAGS="-l hana_vlib.v" test_*.v
+exec ${MAKE:-make} -f ../tools/autotest.mk EXTRA_FLAGS="-l hana_vlib.v -n 300" test_*.v
diff --git a/tests/hana/test_intermout.v b/tests/hana/test_intermout.v
new file mode 100644
index 00000000..88b91ee4
--- /dev/null
+++ b/tests/hana/test_intermout.v
@@ -0,0 +1,418 @@
+
+// test_intermout_always_comb_1_test.v
+module f1_test(a, b, c, d, z);
+input a, b, c, d;
+output z;
+reg z, temp1, temp2;
+
+always @(a or b or c or d)
+begin
+    temp1 = a ^ b;
+	temp2 = c ^ d;
+	z = temp1 ^ temp2;
+end	
+
+endmodule
+
+// test_intermout_always_comb_3_test.v
+module f2_test (in1, in2, out);
+input  in1, in2;
+output  reg out;
+
+always @ ( in1 or in2)
+	if(in1 > in2)
+		out = in1;
+	else
+		out = in2;
+endmodule		
+
+// test_intermout_always_comb_4_test.v
+module f3_test(a, b, c);
+input b, c;
+output reg a;
+
+always @(b or c) begin
+a = b;
+a = c;
+end
+endmodule
+
+// test_intermout_always_comb_5_test.v
+module f4_test(ctrl, in1,  in2, out);
+input ctrl;
+input  in1, in2;
+output  reg out;
+
+always @ (ctrl or in1 or in2)
+	if(ctrl)
+		out = in1 & in2;
+	else 
+		out = in1 | in2;
+endmodule		
+
+// test_intermout_always_ff_3_test.v
+module f5_NonBlockingEx(clk, merge, er, xmit, fddi, claim);
+input clk, merge, er, xmit, fddi;
+output reg claim;
+reg fcr;
+
+always @(posedge clk)
+begin
+    fcr = er | xmit;
+
+	if(merge)
+	    claim = fcr & fddi;
+	else
+	    claim = fddi;
+end
+endmodule
+
+// test_intermout_always_ff_4_test.v
+module f6_FlipFlop(clk, cs, ns);
+input clk;
+input [31:0] cs;
+output [31:0] ns;
+integer is;
+
+always @(posedge clk)
+    is <= cs;
+
+assign ns = is;
+endmodule	
+
+// test_intermout_always_ff_5_test.v
+module f7_FlipFlop(clock, cs, ns);
+input clock;
+input [3:0] cs;
+output reg [3:0] ns;
+reg [3:0] temp;
+
+always @(posedge clock)
+begin
+    temp = cs;
+	ns = temp;
+end	
+
+endmodule	
+
+// test_intermout_always_ff_6_test.v
+module f8_inc(clock, counter);
+
+input clock;
+output reg [3:0] counter;
+always @(posedge clock)
+	counter <= counter + 1;
+endmodule	
+
+// test_intermout_always_ff_8_test.v
+module f9_NegEdgeClock(q, d, clk, reset);
+input d, clk, reset;
+output reg q;
+
+always @(negedge clk or negedge reset)
+    if(!reset)
+	    q <= 1'b0;
+	else	
+        q <= d;
+
+endmodule
+
+// test_intermout_always_ff_9_test.v
+module f10_MyCounter (clock, preset, updown, presetdata, counter);
+input clock, preset, updown;
+input [1: 0] presetdata;
+output reg [1:0] counter;
+
+always @(posedge clock)
+    if(preset)
+	    counter <= presetdata;
+	else
+	    if(updown)
+		    counter <= counter + 1;
+		else
+		    counter <= counter - 1;
+endmodule			
+
+// test_intermout_always_latch_1_test.v
+module f11_test(en, in, out);
+input en;
+input [1:0] in;
+output reg [2:0] out;
+
+always @ (en or in)
+	if(en)
+		out = in + 1;
+endmodule		
+
+// test_intermout_bufrm_1_test.v
+module f12_test(input in, output out);
+//no buffer removal
+assign out = in;
+endmodule
+
+// test_intermout_bufrm_2_test.v
+module f13_test(input in, output out);
+//intermediate buffers should be removed
+wire w1, w2;
+assign w1 = in;
+assign w2 = w1;
+assign out = w2;
+endmodule
+
+// test_intermout_bufrm_6_test.v
+module f14_test(in, out);
+input in;
+output out;
+
+wire w1, w2, w3, w4;
+assign w1 = in;
+assign w2 = w1;
+assign w4 = w3;
+assign out = w4;
+f14_mybuf _f14_mybuf(w2, w3);
+endmodule
+
+module f14_mybuf(in, out);
+input in;
+output out;
+wire w1, w2, w3, w4;
+
+assign w1 = in;
+assign w2 = w1;
+assign out = w2;
+endmodule
+
+
+// test_intermout_bufrm_7_test.v
+module f15_test(in1, in2, out);
+input in1, in2;
+output out;
+// Y with cluster of f15_mybuf instances at the junction
+
+wire w1, w2, w3, w4, w5, w6, w7, w8, w9, w10;
+assign w1 = in1;
+assign w2 = w1;
+assign w5 = in2;
+assign w6 = w5;
+assign w10 = w9;
+assign out = w10;
+
+f15_mybuf _f15_mybuf0(w2, w3);
+f15_mybuf _f15_mybuf1(w3, w4);
+
+f15_mybuf _f15_mybuf2(w6, w7);
+f15_mybuf _f15_mybuf3(w7, w4);
+
+f15_mybuf _f15_mybuf4(w4, w8);
+f15_mybuf _f15_mybuf5(w8, w9);
+endmodule
+
+module f15_mybuf(in, out);
+input in;
+output out;
+wire w1, w2, w3, w4;
+
+assign w1 = in;
+assign w2 = w1;
+assign out = w2;
+endmodule
+
+
+// test_intermout_exprs_add_test.v
+module f16_test(out, in1, in2, vin1, vin2, vout1);
+output out;
+input in1, in2;
+input [1:0] vin1;
+input [2:0] vin2;
+output [3:0] vout1;
+
+assign out = in1 + in2;
+assign vout1 = vin1 + vin2;
+endmodule
+
+// test_intermout_exprs_binlogic_test.v
+module f17_test(in1, in2, vin1, vin2, out, vout, vin3, vin4, vout1 );
+input in1, in2;
+input [1:0] vin1;
+input [3:0] vin2;
+input [1:0] vin3;
+input [3:0] vin4;
+output vout, vout1;
+output out;
+
+assign out = in1 && in2;
+assign vout = vin1 && vin2;
+assign vout1 = vin3 || vin4;
+endmodule
+
+// test_intermout_exprs_bitwiseneg_test.v
+module f18_test(output out, input in, output [1:0] vout, input [1:0] vin);
+
+assign out = ~in;
+assign vout = ~vin;
+endmodule
+
+// test_intermout_exprs_buffer_test.v
+module f19_buffer(in, out, vin, vout);
+input  in;
+output out;
+input [1:0] vin;
+output [1:0] vout;
+
+assign out = in;
+assign vout = vin;
+endmodule
+
+// test_intermout_exprs_condexpr_mux_test.v
+module f20_test(in1, in2, out,  vin1, vin2, vin3, vin4, vout1, vout2, en1, ven1, ven2);
+input in1, in2, en1, ven1;
+input [1:0] ven2;
+output out;
+input [1:0] vin1,  vin2, vin3, vin4;
+output [1:0] vout1, vout2;
+
+assign out = en1 ? in1 : in2;
+assign vout1 = ven1 ? vin1 : vin2;
+assign vout2 = ven2 ? vin3 : vin4;
+endmodule
+
+// test_intermout_exprs_condexpr_tribuf_test.v
+module f21_test(in, out, en, vin1, vout1, en1);
+input in, en, en1;
+output out;
+input [1:0] vin1;
+output [1:0] vout1;
+
+assign out = en ? in : 1'bz;
+assign vout1 = en1 ? vin1 : 2'bzz;
+endmodule
+
+// test_intermout_exprs_constshift_test.v
+module f22_test(in, out, vin, vout, vin1, vout1, vin2, vout2);
+
+input in;
+input [3:0] vin, vin1, vin2;
+output [3:0] vout, vout1, vout2;
+output out;
+
+assign out = in << 1;
+assign vout = vin << 2;
+assign vout1 = vin1 >> 2;
+assign vout2 = vin2 >>> 2;
+endmodule
+
+// test_intermout_exprs_const_test.v
+module f23_test (out, vout);
+output out;
+output [7:0] vout;
+
+assign out = 1'b1;
+assign vout = 9;
+endmodule
+
+// test_intermout_exprs_div_test.v
+module f24_test(out, in1, in2, vin1, vin2, vout1);
+output out;
+input in1, in2;
+input [1:0] vin1;
+input [2:0] vin2;
+output [3:0] vout1;
+
+assign out = in1 / in2;
+assign vout1 = vin1 / vin2;
+endmodule
+
+// test_intermout_exprs_logicneg_test.v
+module f25_test(out, vout, in, vin);
+output out, vout;
+input in;
+input [3:0] vin;
+assign out = !in;
+assign vout = !vin;
+endmodule
+
+// test_intermout_exprs_mod_test.v
+module f26_test(out, in1, in2, vin1, vin2, vout1);
+output out;
+input in1, in2;
+input [1:0] vin1;
+input [2:0] vin2;
+output [3:0] vout1;
+
+assign out = in1 % in2;
+assign vout1 = vin1 % vin2;
+endmodule
+
+// test_intermout_exprs_mul_test.v
+module f27_test(out, in1, in2, vin1, vin2, vout1);
+output out;
+input in1, in2;
+input [1:0] vin1;
+input [2:0] vin2;
+output [3:0] vout1;
+
+assign out = in1 * in2;
+assign vout1 = vin1 * vin2;
+endmodule
+
+// test_intermout_exprs_redand_test.v
+module f28_test(output out, input [1:0] vin, output out1, input [3:0] vin1);
+
+assign out = &vin;
+assign out1 = &vin1;
+endmodule
+
+// test_intermout_exprs_redop_test.v
+module f29_Reduction (A1, A2, A3, A4, A5, A6, Y1, Y2, Y3, Y4, Y5, Y6);
+input [1:0] A1; 
+input [1:0] A2; 
+input [1:0] A3; 
+input [1:0] A4; 
+input [1:0] A5; 
+input [1:0] A6; 
+output Y1, Y2, Y3, Y4, Y5, Y6; 
+//reg Y1, Y2, Y3, Y4, Y5, Y6; 
+assign Y1=&A1; //reduction AND 
+assign Y2=|A2; //reduction OR 
+assign Y3=~&A3; //reduction NAND 
+assign Y4=~|A4; //reduction NOR 
+assign Y5=^A5; //reduction XOR 
+assign Y6=~^A6; //reduction XNOR 
+endmodule
+
+// test_intermout_exprs_sub_test.v
+module f30_test(out, in1, in2, vin1, vin2, vout1);
+output out;
+input in1, in2;
+input [1:0] vin1;
+input [2:0] vin2;
+output [3:0] vout1;
+
+assign out = in1 - in2;
+assign vout1 = vin1 - vin2;
+endmodule
+
+// test_intermout_exprs_unaryminus_test.v
+module f31_test(output out, input in, output [31:0] vout, input [31:0] vin);
+
+assign out = -in;
+assign vout = -vin;
+endmodule
+
+// test_intermout_exprs_unaryplus_test.v
+module f32_test(output out, input in);
+
+assign out = +in;
+endmodule
+
+// test_intermout_exprs_varshift_test.v
+module f33_test(vin0, vout0);
+input [2:0] vin0;
+output reg [7:0] vout0;
+
+wire [7:0] myreg0, myreg1, myreg2;
+integer i;
+assign myreg0 = vout0 << vin0;
+
+assign myreg1 = myreg2 >> i;
+endmodule
diff --git a/tests/hana/test_intermout_always_comb_1_test.v b/tests/hana/test_intermout_always_comb_1_test.v
deleted file mode 100644
index 2d5abc4a..00000000
--- a/tests/hana/test_intermout_always_comb_1_test.v
+++ /dev/null
@@ -1,13 +0,0 @@
-module test(a, b, c, d, z);
-input a, b, c, d;
-output z;
-reg z, temp1, temp2;
-
-always @(a or b or c or d)
-begin
-    temp1 = a ^ b;
-	temp2 = c ^ d;
-	z = temp1 ^ temp2;
-end	
-
-endmodule
diff --git a/tests/hana/test_intermout_always_comb_3_test.v b/tests/hana/test_intermout_always_comb_3_test.v
deleted file mode 100644
index 234407ef..00000000
--- a/tests/hana/test_intermout_always_comb_3_test.v
+++ /dev/null
@@ -1,10 +0,0 @@
-module test (in1, in2, out);
-input  in1, in2;
-output  reg out;
-
-always @ ( in1 or in2)
-	if(in1 > in2)
-		out = in1;
-	else
-		out = in2;
-endmodule		
diff --git a/tests/hana/test_intermout_always_comb_4_test.v b/tests/hana/test_intermout_always_comb_4_test.v
deleted file mode 100644
index b0a94f29..00000000
--- a/tests/hana/test_intermout_always_comb_4_test.v
+++ /dev/null
@@ -1,9 +0,0 @@
-module test(a, b, c);
-input b, c;
-output reg a;
-
-always @(b or c) begin
-a = b;
-a = c;
-end
-endmodule
diff --git a/tests/hana/test_intermout_always_comb_5_test.v b/tests/hana/test_intermout_always_comb_5_test.v
deleted file mode 100644
index 5152781d..00000000
--- a/tests/hana/test_intermout_always_comb_5_test.v
+++ /dev/null
@@ -1,11 +0,0 @@
-module test(ctrl, in1,  in2, out);
-input ctrl;
-input  in1, in2;
-output  reg out;
-
-always @ (ctrl or in1 or in2)
-	if(ctrl)
-		out = in1 & in2;
-	else 
-		out = in1 | in2;
-endmodule		
diff --git a/tests/hana/test_intermout_always_ff_3_test.v b/tests/hana/test_intermout_always_ff_3_test.v
deleted file mode 100644
index ed8630c3..00000000
--- a/tests/hana/test_intermout_always_ff_3_test.v
+++ /dev/null
@@ -1,15 +0,0 @@
-module NonBlockingEx(clk, merge, er, xmit, fddi, claim);
-input clk, merge, er, xmit, fddi;
-output reg claim;
-reg fcr;
-
-always @(posedge clk)
-begin
-    fcr = er | xmit;
-
-	if(merge)
-	    claim = fcr & fddi;
-	else
-	    claim = fddi;
-end
-endmodule
diff --git a/tests/hana/test_intermout_always_ff_4_test.v b/tests/hana/test_intermout_always_ff_4_test.v
deleted file mode 100644
index cac420a4..00000000
--- a/tests/hana/test_intermout_always_ff_4_test.v
+++ /dev/null
@@ -1,11 +0,0 @@
-module FlipFlop(clk, cs, ns);
-input clk;
-input [31:0] cs;
-output [31:0] ns;
-integer is;
-
-always @(posedge clk)
-    is <= cs;
-
-assign ns = is;
-endmodule	
diff --git a/tests/hana/test_intermout_always_ff_5_test.v b/tests/hana/test_intermout_always_ff_5_test.v
deleted file mode 100644
index 669b2a5f..00000000
--- a/tests/hana/test_intermout_always_ff_5_test.v
+++ /dev/null
@@ -1,13 +0,0 @@
-module FlipFlop(clock, cs, ns);
-input clock;
-input [3:0] cs;
-output reg [3:0] ns;
-reg [3:0] temp;
-
-always @(posedge clock)
-begin
-    temp = cs;
-	ns = temp;
-end	
-
-endmodule	
diff --git a/tests/hana/test_intermout_always_ff_6_test.v b/tests/hana/test_intermout_always_ff_6_test.v
deleted file mode 100644
index ad0a0df6..00000000
--- a/tests/hana/test_intermout_always_ff_6_test.v
+++ /dev/null
@@ -1,7 +0,0 @@
-module inc(clock, counter);
-
-input clock;
-output reg [3:0] counter;
-always @(posedge clock)
-	counter <= counter + 1;
-endmodule	
diff --git a/tests/hana/test_intermout_always_ff_8_test.v b/tests/hana/test_intermout_always_ff_8_test.v
deleted file mode 100644
index 0f29ea0a..00000000
--- a/tests/hana/test_intermout_always_ff_8_test.v
+++ /dev/null
@@ -1,11 +0,0 @@
-module NegEdgeClock(q, d, clk, reset);
-input d, clk, reset;
-output reg q;
-
-always @(negedge clk or negedge reset)
-    if(!reset)
-	    q <= 1'b0;
-	else	
-        q <= d;
-
-endmodule
diff --git a/tests/hana/test_intermout_always_ff_9_test.v b/tests/hana/test_intermout_always_ff_9_test.v
deleted file mode 100644
index f1f13bbe..00000000
--- a/tests/hana/test_intermout_always_ff_9_test.v
+++ /dev/null
@@ -1,14 +0,0 @@
-module MyCounter (clock, preset, updown, presetdata, counter);
-input clock, preset, updown;
-input [1: 0] presetdata;
-output reg [1:0] counter;
-
-always @(posedge clock)
-    if(preset)
-	    counter <= presetdata;
-	else
-	    if(updown)
-		    counter <= counter + 1;
-		else
-		    counter <= counter - 1;
-endmodule			
diff --git a/tests/hana/test_intermout_always_latch_1_test.v b/tests/hana/test_intermout_always_latch_1_test.v
deleted file mode 100644
index a83be20d..00000000
--- a/tests/hana/test_intermout_always_latch_1_test.v
+++ /dev/null
@@ -1,9 +0,0 @@
-module test(en, in, out);
-input en;
-input [1:0] in;
-output reg [2:0] out;
-
-always @ (en or in)
-	if(en)
-		out = in + 1;
-endmodule		
diff --git a/tests/hana/test_intermout_bufrm_1_test.v b/tests/hana/test_intermout_bufrm_1_test.v
deleted file mode 100644
index 8e3d4222..00000000
--- a/tests/hana/test_intermout_bufrm_1_test.v
+++ /dev/null
@@ -1,4 +0,0 @@
-module test(input in, output out);
-//no buffer removal
-assign out = in;
-endmodule
diff --git a/tests/hana/test_intermout_bufrm_2_test.v b/tests/hana/test_intermout_bufrm_2_test.v
deleted file mode 100644
index 853f1dc9..00000000
--- a/tests/hana/test_intermout_bufrm_2_test.v
+++ /dev/null
@@ -1,7 +0,0 @@
-module test(input in, output out);
-//intermediate buffers should be removed
-wire w1, w2;
-assign w1 = in;
-assign w2 = w1;
-assign out = w2;
-endmodule
diff --git a/tests/hana/test_intermout_bufrm_6_test.v b/tests/hana/test_intermout_bufrm_6_test.v
deleted file mode 100644
index d4f3878d..00000000
--- a/tests/hana/test_intermout_bufrm_6_test.v
+++ /dev/null
@@ -1,22 +0,0 @@
-module test(in, out);
-input in;
-output out;
-
-wire w1, w2, w3, w4;
-assign w1 = in;
-assign w2 = w1;
-assign w4 = w3;
-assign out = w4;
-mybuf _mybuf(w2, w3);
-endmodule
-
-module mybuf(in, out);
-input in;
-output out;
-wire w1, w2, w3, w4;
-
-assign w1 = in;
-assign w2 = w1;
-assign out = w2;
-endmodule
-
diff --git a/tests/hana/test_intermout_bufrm_7_test.v b/tests/hana/test_intermout_bufrm_7_test.v
deleted file mode 100644
index 7b651302..00000000
--- a/tests/hana/test_intermout_bufrm_7_test.v
+++ /dev/null
@@ -1,33 +0,0 @@
-module test(in1, in2, out);
-input in1, in2;
-output out;
-// Y with cluster of mybuf instances at the junction
-
-wire w1, w2, w3, w4, w5, w6, w7, w8, w9, w10;
-assign w1 = in1;
-assign w2 = w1;
-assign w5 = in2;
-assign w6 = w5;
-assign w10 = w9;
-assign out = w10;
-
-mybuf _mybuf0(w2, w3);
-mybuf _mybuf1(w3, w4);
-
-mybuf _mybuf2(w6, w7);
-mybuf _mybuf3(w7, w4);
-
-mybuf _mybuf4(w4, w8);
-mybuf _mybuf5(w8, w9);
-endmodule
-
-module mybuf(in, out);
-input in;
-output out;
-wire w1, w2, w3, w4;
-
-assign w1 = in;
-assign w2 = w1;
-assign out = w2;
-endmodule
-
diff --git a/tests/hana/test_intermout_exprs_add_test.v b/tests/hana/test_intermout_exprs_add_test.v
deleted file mode 100644
index ec70f347..00000000
--- a/tests/hana/test_intermout_exprs_add_test.v
+++ /dev/null
@@ -1,10 +0,0 @@
-module test(out, in1, in2, vin1, vin2, vout1);
-output out;
-input in1, in2;
-input [1:0] vin1;
-input [2:0] vin2;
-output [3:0] vout1;
-
-assign out = in1 + in2;
-assign vout1 = vin1 + vin2;
-endmodule
diff --git a/tests/hana/test_intermout_exprs_binlogic_test.v b/tests/hana/test_intermout_exprs_binlogic_test.v
deleted file mode 100644
index eec8c4b1..00000000
--- a/tests/hana/test_intermout_exprs_binlogic_test.v
+++ /dev/null
@@ -1,13 +0,0 @@
-module test(in1, in2, vin1, vin2, out, vout, vin3, vin4, vout1 );
-input in1, in2;
-input [1:0] vin1;
-input [3:0] vin2;
-input [1:0] vin3;
-input [3:0] vin4;
-output vout, vout1;
-output out;
-
-assign out = in1 && in2;
-assign vout = vin1 && vin2;
-assign vout1 = vin3 || vin4;
-endmodule
diff --git a/tests/hana/test_intermout_exprs_bitwiseneg_test.v b/tests/hana/test_intermout_exprs_bitwiseneg_test.v
deleted file mode 100644
index 5b62bef0..00000000
--- a/tests/hana/test_intermout_exprs_bitwiseneg_test.v
+++ /dev/null
@@ -1,5 +0,0 @@
-module test(output out, input in, output [1:0] vout, input [1:0] vin);
-
-assign out = ~in;
-assign vout = ~vin;
-endmodule
diff --git a/tests/hana/test_intermout_exprs_buffer_test.v b/tests/hana/test_intermout_exprs_buffer_test.v
deleted file mode 100644
index 2b4cbc3e..00000000
--- a/tests/hana/test_intermout_exprs_buffer_test.v
+++ /dev/null
@@ -1,9 +0,0 @@
-module buffer(in, out, vin, vout);
-input  in;
-output out;
-input [1:0] vin;
-output [1:0] vout;
-
-assign out = in;
-assign vout = vin;
-endmodule
diff --git a/tests/hana/test_intermout_exprs_condexpr_mux_test.v b/tests/hana/test_intermout_exprs_condexpr_mux_test.v
deleted file mode 100644
index 11006e8b..00000000
--- a/tests/hana/test_intermout_exprs_condexpr_mux_test.v
+++ /dev/null
@@ -1,11 +0,0 @@
-module test(in1, in2, out,  vin1, vin2, vin3, vin4, vout1, vout2, en1, ven1, ven2);
-input in1, in2, en1, ven1;
-input [1:0] ven2;
-output out;
-input [1:0] vin1,  vin2, vin3, vin4;
-output [1:0] vout1, vout2;
-
-assign out = en1 ? in1 : in2;
-assign vout1 = ven1 ? vin1 : vin2;
-assign vout2 = ven2 ? vin3 : vin4;
-endmodule
diff --git a/tests/hana/test_intermout_exprs_condexpr_tribuf_test.v b/tests/hana/test_intermout_exprs_condexpr_tribuf_test.v
deleted file mode 100644
index 5b778fe9..00000000
--- a/tests/hana/test_intermout_exprs_condexpr_tribuf_test.v
+++ /dev/null
@@ -1,9 +0,0 @@
-module test(in, out, en, vin1, vout1, en1);
-input in, en, en1;
-output out;
-input [1:0] vin1;
-output [1:0] vout1;
-
-assign out = en ? in : 1'bz;
-assign vout1 = en1 ? vin1 : 2'bzz;
-endmodule
diff --git a/tests/hana/test_intermout_exprs_const_test.v b/tests/hana/test_intermout_exprs_const_test.v
deleted file mode 100644
index 484d8103..00000000
--- a/tests/hana/test_intermout_exprs_const_test.v
+++ /dev/null
@@ -1,7 +0,0 @@
-module test (out, vout);
-output out;
-output [7:0] vout;
-
-assign out = 1'b1;
-assign vout = 9;
-endmodule
diff --git a/tests/hana/test_intermout_exprs_constshift_test.v b/tests/hana/test_intermout_exprs_constshift_test.v
deleted file mode 100644
index eb21315d..00000000
--- a/tests/hana/test_intermout_exprs_constshift_test.v
+++ /dev/null
@@ -1,12 +0,0 @@
-module test(in, out, vin, vout, vin1, vout1, vin2, vout2);
-
-input in;
-input [3:0] vin, vin1, vin2;
-output [3:0] vout, vout1, vout2;
-output out;
-
-assign out = in << 1;
-assign vout = vin << 2;
-assign vout1 = vin1 >> 2;
-assign vout2 = vin2 >>> 2;
-endmodule
diff --git a/tests/hana/test_intermout_exprs_div_test.v b/tests/hana/test_intermout_exprs_div_test.v
deleted file mode 100644
index 21765fcd..00000000
--- a/tests/hana/test_intermout_exprs_div_test.v
+++ /dev/null
@@ -1,10 +0,0 @@
-module test(out, in1, in2, vin1, vin2, vout1);
-output out;
-input in1, in2;
-input [1:0] vin1;
-input [2:0] vin2;
-output [3:0] vout1;
-
-assign out = in1 / in2;
-assign vout1 = vin1 / vin2;
-endmodule
diff --git a/tests/hana/test_intermout_exprs_logicneg_test.v b/tests/hana/test_intermout_exprs_logicneg_test.v
deleted file mode 100644
index b45b32b9..00000000
--- a/tests/hana/test_intermout_exprs_logicneg_test.v
+++ /dev/null
@@ -1,7 +0,0 @@
-module test(out, vout, in, vin);
-output out, vout;
-input in;
-input [3:0] vin;
-assign out = !in;
-assign vout = !vin;
-endmodule
diff --git a/tests/hana/test_intermout_exprs_mod_test.v b/tests/hana/test_intermout_exprs_mod_test.v
deleted file mode 100644
index cea6b02d..00000000
--- a/tests/hana/test_intermout_exprs_mod_test.v
+++ /dev/null
@@ -1,10 +0,0 @@
-module test(out, in1, in2, vin1, vin2, vout1);
-output out;
-input in1, in2;
-input [1:0] vin1;
-input [2:0] vin2;
-output [3:0] vout1;
-
-assign out = in1 % in2;
-assign vout1 = vin1 % vin2;
-endmodule
diff --git a/tests/hana/test_intermout_exprs_mul_test.v b/tests/hana/test_intermout_exprs_mul_test.v
deleted file mode 100644
index f9973dad..00000000
--- a/tests/hana/test_intermout_exprs_mul_test.v
+++ /dev/null
@@ -1,10 +0,0 @@
-module test(out, in1, in2, vin1, vin2, vout1);
-output out;
-input in1, in2;
-input [1:0] vin1;
-input [2:0] vin2;
-output [3:0] vout1;
-
-assign out = in1 * in2;
-assign vout1 = vin1 * vin2;
-endmodule
diff --git a/tests/hana/test_intermout_exprs_redand_test.v b/tests/hana/test_intermout_exprs_redand_test.v
deleted file mode 100644
index 35fdf73a..00000000
--- a/tests/hana/test_intermout_exprs_redand_test.v
+++ /dev/null
@@ -1,5 +0,0 @@
-module test(output out, input [1:0] vin, output out1, input [3:0] vin1);
-
-assign out = &vin;
-assign out1 = &vin1;
-endmodule
diff --git a/tests/hana/test_intermout_exprs_redop_test.v b/tests/hana/test_intermout_exprs_redop_test.v
deleted file mode 100644
index 93fdb2e5..00000000
--- a/tests/hana/test_intermout_exprs_redop_test.v
+++ /dev/null
@@ -1,16 +0,0 @@
-module Reduction (A1, A2, A3, A4, A5, A6, Y1, Y2, Y3, Y4, Y5, Y6);
-input [1:0] A1; 
-input [1:0] A2; 
-input [1:0] A3; 
-input [1:0] A4; 
-input [1:0] A5; 
-input [1:0] A6; 
-output Y1, Y2, Y3, Y4, Y5, Y6; 
-//reg Y1, Y2, Y3, Y4, Y5, Y6; 
-assign Y1=&A1; //reduction AND 
-assign Y2=|A2; //reduction OR 
-assign Y3=~&A3; //reduction NAND 
-assign Y4=~|A4; //reduction NOR 
-assign Y5=^A5; //reduction XOR 
-assign Y6=~^A6; //reduction XNOR 
-endmodule
diff --git a/tests/hana/test_intermout_exprs_sub_test.v b/tests/hana/test_intermout_exprs_sub_test.v
deleted file mode 100644
index 06e3a814..00000000
--- a/tests/hana/test_intermout_exprs_sub_test.v
+++ /dev/null
@@ -1,10 +0,0 @@
-module test(out, in1, in2, vin1, vin2, vout1);
-output out;
-input in1, in2;
-input [1:0] vin1;
-input [2:0] vin2;
-output [3:0] vout1;
-
-assign out = in1 - in2;
-assign vout1 = vin1 - vin2;
-endmodule
diff --git a/tests/hana/test_intermout_exprs_unaryminus_test.v b/tests/hana/test_intermout_exprs_unaryminus_test.v
deleted file mode 100644
index ee3f229a..00000000
--- a/tests/hana/test_intermout_exprs_unaryminus_test.v
+++ /dev/null
@@ -1,5 +0,0 @@
-module test(output out, input in, output [31:0] vout, input [31:0] vin);
-
-assign out = -in;
-assign vout = -vin;
-endmodule
diff --git a/tests/hana/test_intermout_exprs_unaryplus_test.v b/tests/hana/test_intermout_exprs_unaryplus_test.v
deleted file mode 100644
index 07be5b24..00000000
--- a/tests/hana/test_intermout_exprs_unaryplus_test.v
+++ /dev/null
@@ -1,4 +0,0 @@
-module test(output out, input in);
-
-assign out = +in;
-endmodule
diff --git a/tests/hana/test_intermout_exprs_varshift_test.v b/tests/hana/test_intermout_exprs_varshift_test.v
deleted file mode 100644
index 2ca35c09..00000000
--- a/tests/hana/test_intermout_exprs_varshift_test.v
+++ /dev/null
@@ -1,10 +0,0 @@
-module test(vin0, vout0);
-input [2:0] vin0;
-output reg [7:0] vout0;
-
-wire [7:0] myreg0, myreg1, myreg2;
-integer i;
-assign myreg0 = vout0 << vin0;
-
-assign myreg1 = myreg2 >> i;
-endmodule
diff --git a/tests/hana/test_parse2synthtrans.v b/tests/hana/test_parse2synthtrans.v
new file mode 100644
index 00000000..a1c0bfdb
--- /dev/null
+++ b/tests/hana/test_parse2synthtrans.v
@@ -0,0 +1,117 @@
+
+// test_parse2synthtrans_behavopt_1_test.v
+module f1_test(in, out, clk, reset);
+input in, reset;
+output reg out;
+input clk;
+reg signed [3:0] a;
+reg signed [3:0] b;
+reg signed [3:0] c;
+reg [5:0] d;
+reg [5:0] e;
+
+always @(clk or reset) begin
+    a = -4;
+    b = 2;
+    c = a + b;
+    d = a + b + c;
+    d = d*d;
+    if(b)
+        e = d*d;
+    else 
+        e = d + d;
+end
+endmodule
+
+// test_parse2synthtrans_case_1_test.v
+module f2_demultiplexer1_to_4 (out0, out1, out2, out3, in, s1, s0);
+output out0, out1, out2, out3;
+reg out0, out1, out2, out3;
+input in;
+input s1, s0;
+reg [3:0] encoding;
+reg [1:0] state;
+   always @(encoding) begin
+        case (encoding)
+        4'bxx11: state = 1;
+        4'bx0xx: state = 3;
+        4'b11xx: state = 4;
+        4'bx1xx: state = 2;
+        4'bxx1x: state = 1;
+        4'bxxx1: state = 0;
+        default: state = 0;
+        endcase
+   end
+   
+   always @(encoding) begin
+        case (encoding)
+        4'b0000: state = 1;
+        default: state = 0;
+        endcase
+   end
+endmodule
+
+// test_parse2synthtrans_contassign_1_test.v
+module f3_test(in, out);
+
+input wire in;
+output  out;
+assign out = (in+in);
+assign out = 74;
+endmodule
+
+// test_parse2synthtrans_module_basic0_test.v
+module f4_test;
+endmodule
+
+// test_parse2synthtrans_operators_1_test.v
+module f5_test(in, out);
+input in;
+output out;
+parameter p1 = 10;
+parameter p2 = 5;
+
+assign out = +p1;
+assign out = -p2;
+assign out = p1 + p2;
+assign out = p1 - p2;
+endmodule
+
+// test_parse2synthtrans_param_1_test.v
+module f6_test(in, out);
+input in;
+output out;
+parameter p = 10;
+
+assign out = p;
+endmodule
+
+// test_parse2synthtrans_port_scalar_1_test.v
+module f7_test(in, out, io);
+inout io;
+output out;
+input in;
+
+endmodule
+
+// test_parse2synthtrans_port_vector_1_test.v
+module f8_test(in1, in2, out1, out2, io1, io2);
+inout [1:0] io1;
+inout [0:1] io2;
+output [1:0] out1;
+output [0:1] out2;
+input [1:0] in1;
+input [0:1] in2;
+
+endmodule
+
+// test_parse2synthtrans_v2k_comb_logic_sens_list_test.v
+module f9_test(q, d, clk, reset);
+output reg q;
+input d, clk, reset;
+
+always @ (posedge clk, negedge reset)
+	if(!reset) q <= 0;
+	else q <= d;
+
+endmodule
diff --git a/tests/hana/test_parse2synthtrans_behavopt_1_test.v b/tests/hana/test_parse2synthtrans_behavopt_1_test.v
deleted file mode 100644
index c825739c..00000000
--- a/tests/hana/test_parse2synthtrans_behavopt_1_test.v
+++ /dev/null
@@ -1,22 +0,0 @@
-module test(in, out, clk, reset);
-input in, reset;
-output reg out;
-input clk;
-reg signed [3:0] a;
-reg signed [3:0] b;
-reg signed [3:0] c;
-reg [5:0] d;
-reg [5:0] e;
-
-always @(clk or reset) begin
-    a = -4;
-    b = 2;
-    c = a + b;
-    d = a + b + c;
-    d = d*d;
-    if(b)
-        e = d*d;
-    else 
-        e = d + d;
-end
-endmodule
diff --git a/tests/hana/test_parse2synthtrans_case_1_test.v b/tests/hana/test_parse2synthtrans_case_1_test.v
deleted file mode 100644
index 348c566a..00000000
--- a/tests/hana/test_parse2synthtrans_case_1_test.v
+++ /dev/null
@@ -1,26 +0,0 @@
-module demultiplexer1_to_4 (out0, out1, out2, out3, in, s1, s0);
-output out0, out1, out2, out3;
-reg out0, out1, out2, out3;
-input in;
-input s1, s0;
-reg [3:0] encoding;
-reg [1:0] state;
-   always @(encoding) begin
-        case (encoding)
-        4'bxx11: state = 1;
-        4'bx0xx: state = 3;
-        4'b11xx: state = 4;
-        4'bx1xx: state = 2;
-        4'bxx1x: state = 1;
-        4'bxxx1: state = 0;
-        default: state = 0;
-        endcase
-   end
-   
-   always @(encoding) begin
-        case (encoding)
-        4'b0000: state = 1;
-        default: state = 0;
-        endcase
-   end
-endmodule
diff --git a/tests/hana/test_parse2synthtrans_contassign_1_test.v b/tests/hana/test_parse2synthtrans_contassign_1_test.v
deleted file mode 100644
index 78bf0077..00000000
--- a/tests/hana/test_parse2synthtrans_contassign_1_test.v
+++ /dev/null
@@ -1,7 +0,0 @@
-module test(in, out);
-
-input wire in;
-output  out;
-assign out = (in+in);
-assign out = 74;
-endmodule
diff --git a/tests/hana/test_parse2synthtrans_module_basic0_test.v b/tests/hana/test_parse2synthtrans_module_basic0_test.v
deleted file mode 100644
index 67a272df..00000000
--- a/tests/hana/test_parse2synthtrans_module_basic0_test.v
+++ /dev/null
@@ -1,2 +0,0 @@
-module test;
-endmodule
diff --git a/tests/hana/test_parse2synthtrans_operators_1_test.v b/tests/hana/test_parse2synthtrans_operators_1_test.v
deleted file mode 100644
index 93b5691f..00000000
--- a/tests/hana/test_parse2synthtrans_operators_1_test.v
+++ /dev/null
@@ -1,11 +0,0 @@
-module test(in, out);
-input in;
-output out;
-parameter p1 = 10;
-parameter p2 = 5;
-
-assign out = +p1;
-assign out = -p2;
-assign out = p1 + p2;
-assign out = p1 - p2;
-endmodule
diff --git a/tests/hana/test_parse2synthtrans_param_1_test.v b/tests/hana/test_parse2synthtrans_param_1_test.v
deleted file mode 100644
index 146eedf4..00000000
--- a/tests/hana/test_parse2synthtrans_param_1_test.v
+++ /dev/null
@@ -1,7 +0,0 @@
-module test(in, out);
-input in;
-output out;
-parameter p = 10;
-
-assign out = p;
-endmodule
diff --git a/tests/hana/test_parse2synthtrans_port_scalar_1_test.v b/tests/hana/test_parse2synthtrans_port_scalar_1_test.v
deleted file mode 100644
index 8cdf495a..00000000
--- a/tests/hana/test_parse2synthtrans_port_scalar_1_test.v
+++ /dev/null
@@ -1,6 +0,0 @@
-module test(in, out, io);
-inout io;
-output out;
-input in;
-
-endmodule
diff --git a/tests/hana/test_parse2synthtrans_port_vector_1_test.v b/tests/hana/test_parse2synthtrans_port_vector_1_test.v
deleted file mode 100644
index a740282b..00000000
--- a/tests/hana/test_parse2synthtrans_port_vector_1_test.v
+++ /dev/null
@@ -1,9 +0,0 @@
-module test(in1, in2, out1, out2, io1, io2);
-inout [1:0] io1;
-inout [0:1] io2;
-output [1:0] out1;
-output [0:1] out2;
-input [1:0] in1;
-input [0:1] in2;
-
-endmodule
diff --git a/tests/hana/test_parse2synthtrans_v2k_comb_logic_sens_list_test.v b/tests/hana/test_parse2synthtrans_v2k_comb_logic_sens_list_test.v
deleted file mode 100644
index 50f1d353..00000000
--- a/tests/hana/test_parse2synthtrans_v2k_comb_logic_sens_list_test.v
+++ /dev/null
@@ -1,9 +0,0 @@
-module test(q, d, clk, reset);
-output reg q;
-input d, clk, reset;
-
-always @ (posedge clk, negedge reset)
-	if(!reset) q <= 0;
-	else q <= d;
-
-endmodule
diff --git a/tests/hana/test_parser.v b/tests/hana/test_parser.v
new file mode 100644
index 00000000..c7305356
--- /dev/null
+++ b/tests/hana/test_parser.v
@@ -0,0 +1,87 @@
+
+// test_parser_constructs_module_basic1_test.v
+module f1_test;
+endmodule
+
+// test_parser_constructs_param_basic0_test.v
+module f2_test #( parameter v2kparam = 5)
+(in, out, io, vin, vout, vio);
+input in;
+output out;
+inout io;
+input [3:0] vin;
+output [v2kparam:0] vout;
+inout [0:3] vio;
+parameter myparam = 10;
+endmodule
+
+// test_parser_constructs_port_basic0_test.v
+module f3_test(in, out, io, vin, vout, vio);
+input in;
+output out;
+inout io;
+input [3:0] vin;
+output [3:0] vout;
+inout [0:3] vio;
+endmodule
+
+// test_parser_directives_define_simpledef_test.v
+`define parvez ahmad
+`define  WIRE wire
+`define TEN 10
+
+module f4_`parvez();
+parameter param = `TEN;
+`WIRE w;
+assign w = `TEN;
+endmodule
+
+// test_parser_misc_operators_test.v
+module f5_test(out, i0, i1, i2, i3, s1, s0);
+output out;
+input i0, i1, i2, i3;
+input s1, s0;
+
+assign out = (~s1 & s0 & i0) |
+			 (~s1 & s0 & i1) |
+			 (s1 & ~s0 & i2) |
+			 (s1 & s0 & i3);
+
+endmodule
+
+module f5_ternaryop(out, i0, i1, i2, i3, s1, s0);
+output out;
+input i0, i1, i2, i3;
+input s1, s0;
+
+assign out = s1 ? (s0 ? i3 : i2) : (s0 ? i1 : i0);
+
+endmodule
+
+module f5_fulladd4(sum, c_out, a, b, c_in);
+output [3:0] sum;
+output c_out;
+input [3:0] a, b;
+input c_in;
+
+assign {c_out, sum} = a + b + c_in;
+endmodule
+
+// test_parser_v2k_comb_port_data_type_test.v
+module f6_adder(sum , co, a, b, ci);
+output	reg		[31:0]	sum;
+output	reg				co;
+input	wire	[31:0]	a, b;
+input wire				ci;
+endmodule
+
+// test_parser_v2k_comma_sep_sens_list_test.v
+module f7_test(q, d, clk, reset);
+output reg q;
+input d, clk, reset;
+
+always @ (posedge clk, negedge reset)
+	if(!reset) q <= 0;
+	else q <= d;
+
+endmodule
diff --git a/tests/hana/test_parser_constructs_module_basic1_test.v b/tests/hana/test_parser_constructs_module_basic1_test.v
deleted file mode 100644
index 67a272df..00000000
--- a/tests/hana/test_parser_constructs_module_basic1_test.v
+++ /dev/null
@@ -1,2 +0,0 @@
-module test;
-endmodule
diff --git a/tests/hana/test_parser_constructs_param_basic0_test.v b/tests/hana/test_parser_constructs_param_basic0_test.v
deleted file mode 100644
index fd679230..00000000
--- a/tests/hana/test_parser_constructs_param_basic0_test.v
+++ /dev/null
@@ -1,10 +0,0 @@
-module test #( parameter v2kparam = 5)
-(in, out, io, vin, vout, vio);
-input in;
-output out;
-inout io;
-input [3:0] vin;
-output [v2kparam:0] vout;
-inout [0:3] vio;
-parameter myparam = 10;
-endmodule
diff --git a/tests/hana/test_parser_constructs_port_basic0_test.v b/tests/hana/test_parser_constructs_port_basic0_test.v
deleted file mode 100644
index 8478e31d..00000000
--- a/tests/hana/test_parser_constructs_port_basic0_test.v
+++ /dev/null
@@ -1,8 +0,0 @@
-module test(in, out, io, vin, vout, vio);
-input in;
-output out;
-inout io;
-input [3:0] vin;
-output [3:0] vout;
-inout [0:3] vio;
-endmodule
diff --git a/tests/hana/test_parser_directives_define_simpledef_test.v b/tests/hana/test_parser_directives_define_simpledef_test.v
deleted file mode 100644
index 4a5d2345..00000000
--- a/tests/hana/test_parser_directives_define_simpledef_test.v
+++ /dev/null
@@ -1,9 +0,0 @@
-`define parvez ahmad
-`define  WIRE wire
-`define TEN 10
-
-module `parvez();
-parameter param = `TEN;
-`WIRE w;
-assign w = `TEN;
-endmodule
diff --git a/tests/hana/test_parser_misc_operators_test.v b/tests/hana/test_parser_misc_operators_test.v
deleted file mode 100644
index 8fe8e7ba..00000000
--- a/tests/hana/test_parser_misc_operators_test.v
+++ /dev/null
@@ -1,29 +0,0 @@
-module test(out, i0, i1, i2, i3, s1, s0);
-output out;
-input i0, i1, i2, i3;
-input s1, s0;
-
-assign out = (~s1 & s0 & i0) |
-			 (~s1 & s0 & i1) |
-			 (s1 & ~s0 & i2) |
-			 (s1 & s0 & i3);
-
-endmodule
-
-module ternaryop(out, i0, i1, i2, i3, s1, s0);
-output out;
-input i0, i1, i2, i3;
-input s1, s0;
-
-assign out = s1 ? (s0 ? i3 : i2) : (s0 ? i1 : i0);
-
-endmodule
-
-module fulladd4(sum, c_out, a, b, c_in);
-output [3:0] sum;
-output c_out;
-input [3:0] a, b;
-input c_in;
-
-assign {c_out, sum} = a + b + c_in;
-endmodule
diff --git a/tests/hana/test_parser_v2k_comb_port_data_type_test.v b/tests/hana/test_parser_v2k_comb_port_data_type_test.v
deleted file mode 100644
index 099585b5..00000000
--- a/tests/hana/test_parser_v2k_comb_port_data_type_test.v
+++ /dev/null
@@ -1,6 +0,0 @@
-module adder(sum , co, a, b, ci);
-output	reg		[31:0]	sum;
-output	reg				co;
-input	wire	[31:0]	a, b;
-input wire				ci;
-endmodule
diff --git a/tests/hana/test_parser_v2k_comma_sep_sens_list_test.v b/tests/hana/test_parser_v2k_comma_sep_sens_list_test.v
deleted file mode 100644
index 50f1d353..00000000
--- a/tests/hana/test_parser_v2k_comma_sep_sens_list_test.v
+++ /dev/null
@@ -1,9 +0,0 @@
-module test(q, d, clk, reset);
-output reg q;
-input d, clk, reset;
-
-always @ (posedge clk, negedge reset)
-	if(!reset) q <= 0;
-	else q <= d;
-
-endmodule
diff --git a/tests/hana/test_simulation_always.v b/tests/hana/test_simulation_always.v
new file mode 100644
index 00000000..3ee75313
--- /dev/null
+++ b/tests/hana/test_simulation_always.v
@@ -0,0 +1,135 @@
+
+// test_simulation_always_15_test.v
+module f1_test(input [1:0] in, output reg [1:0] out);
+
+always @(in)
+    out = in;
+endmodule	
+
+// test_simulation_always_17_test.v
+module f2_test(a, b, c, d, z);
+input a, b, c, d;
+output z;
+reg z, temp1, temp2;
+
+always @(a or b or c or d)
+begin
+    temp1 = a ^ b;
+	temp2 = c ^ d;
+	z = temp1 ^ temp2;
+end	
+
+endmodule
+
+// test_simulation_always_18_test.v
+module f3_test (in1, in2, out);
+input  in1, in2;
+output  reg out;
+
+always @ ( in1 or in2)
+	if(in1 > in2)
+		out = in1;
+	else
+		out = in2;
+endmodule		
+
+// test_simulation_always_19_test.v
+module f4_test(ctrl, in1,  in2, out);
+input ctrl;
+input  in1, in2;
+output  reg out;
+
+always @ (ctrl or in1 or in2)
+	if(ctrl)
+		out = in1 & in2;
+	else 
+		out = in1 | in2;
+endmodule		
+
+// test_simulation_always_1_test.v
+module f5_test(input in, output reg out);
+
+always @(in)
+    out = in;
+endmodule	
+
+// test_simulation_always_20_test.v
+module f6_NonBlockingEx(clk, merge, er, xmit, fddi, claim);
+input clk, merge, er, xmit, fddi;
+output reg claim;
+reg fcr;
+
+always @(posedge clk)
+begin
+    fcr <= er | xmit;
+
+	if(merge)
+	    claim <= fcr & fddi;
+	else
+	    claim <= fddi;
+end
+endmodule
+
+// test_simulation_always_21_test.v
+module f7_FlipFlop(clk, cs, ns);
+input clk;
+input [7:0] cs;
+output [7:0] ns;
+integer is;
+
+always @(posedge clk)
+    is <= cs;
+
+assign ns = is;
+endmodule	
+
+// test_simulation_always_22_test.v
+module f8_inc(clock, counter);
+
+input clock;
+output reg [7:0] counter;
+always @(posedge clock)
+	counter <= counter + 1;
+endmodule	
+
+// test_simulation_always_23_test.v
+module f9_MyCounter (clock, preset, updown, presetdata, counter);
+input clock, preset, updown;
+input [1: 0] presetdata;
+output reg [1:0] counter;
+
+always @(posedge clock)
+    if(preset)
+	    counter <= presetdata;
+	else
+	    if(updown)
+		    counter <= counter + 1;
+		else
+		    counter <= counter - 1;
+endmodule			
+
+// test_simulation_always_27_test.v
+module f10_FlipFlop(clock, cs, ns);
+input clock;
+input cs;
+output reg ns;
+reg temp;
+
+always @(posedge clock)
+begin
+    temp <= cs;
+	ns <= temp;
+end	
+
+endmodule	
+
+// test_simulation_always_29_test.v
+module f11_test(input in, output reg [1:0] out);
+
+    always @(in)
+    begin
+        out = in;
+        out = out + in;
+    end
+
+endmodule
diff --git a/tests/hana/test_simulation_always_15_test.v b/tests/hana/test_simulation_always_15_test.v
deleted file mode 100644
index 5c5fed5b..00000000
--- a/tests/hana/test_simulation_always_15_test.v
+++ /dev/null
@@ -1,5 +0,0 @@
-module test(input [1:0] in, output reg [1:0] out);
-
-always @(in)
-    out = in;
-endmodule	
diff --git a/tests/hana/test_simulation_always_17_test.v b/tests/hana/test_simulation_always_17_test.v
deleted file mode 100644
index 2d5abc4a..00000000
--- a/tests/hana/test_simulation_always_17_test.v
+++ /dev/null
@@ -1,13 +0,0 @@
-module test(a, b, c, d, z);
-input a, b, c, d;
-output z;
-reg z, temp1, temp2;
-
-always @(a or b or c or d)
-begin
-    temp1 = a ^ b;
-	temp2 = c ^ d;
-	z = temp1 ^ temp2;
-end	
-
-endmodule
diff --git a/tests/hana/test_simulation_always_18_test.v b/tests/hana/test_simulation_always_18_test.v
deleted file mode 100644
index 234407ef..00000000
--- a/tests/hana/test_simulation_always_18_test.v
+++ /dev/null
@@ -1,10 +0,0 @@
-module test (in1, in2, out);
-input  in1, in2;
-output  reg out;
-
-always @ ( in1 or in2)
-	if(in1 > in2)
-		out = in1;
-	else
-		out = in2;
-endmodule		
diff --git a/tests/hana/test_simulation_always_19_test.v b/tests/hana/test_simulation_always_19_test.v
deleted file mode 100644
index 5152781d..00000000
--- a/tests/hana/test_simulation_always_19_test.v
+++ /dev/null
@@ -1,11 +0,0 @@
-module test(ctrl, in1,  in2, out);
-input ctrl;
-input  in1, in2;
-output  reg out;
-
-always @ (ctrl or in1 or in2)
-	if(ctrl)
-		out = in1 & in2;
-	else 
-		out = in1 | in2;
-endmodule		
diff --git a/tests/hana/test_simulation_always_1_test.v b/tests/hana/test_simulation_always_1_test.v
deleted file mode 100644
index 211369cb..00000000
--- a/tests/hana/test_simulation_always_1_test.v
+++ /dev/null
@@ -1,5 +0,0 @@
-module test(input in, output reg out);
-
-always @(in)
-    out = in;
-endmodule	
diff --git a/tests/hana/test_simulation_always_20_test.v b/tests/hana/test_simulation_always_20_test.v
deleted file mode 100644
index 6b3e861d..00000000
--- a/tests/hana/test_simulation_always_20_test.v
+++ /dev/null
@@ -1,15 +0,0 @@
-module NonBlockingEx(clk, merge, er, xmit, fddi, claim);
-input clk, merge, er, xmit, fddi;
-output reg claim;
-reg fcr;
-
-always @(posedge clk)
-begin
-    fcr <= er | xmit;
-
-	if(merge)
-	    claim <= fcr & fddi;
-	else
-	    claim <= fddi;
-end
-endmodule
diff --git a/tests/hana/test_simulation_always_21_test.v b/tests/hana/test_simulation_always_21_test.v
deleted file mode 100644
index 6c47b4bd..00000000
--- a/tests/hana/test_simulation_always_21_test.v
+++ /dev/null
@@ -1,11 +0,0 @@
-module FlipFlop(clk, cs, ns);
-input clk;
-input [7:0] cs;
-output [7:0] ns;
-integer is;
-
-always @(posedge clk)
-    is <= cs;
-
-assign ns = is;
-endmodule	
diff --git a/tests/hana/test_simulation_always_22_test.v b/tests/hana/test_simulation_always_22_test.v
deleted file mode 100644
index 8d91f815..00000000
--- a/tests/hana/test_simulation_always_22_test.v
+++ /dev/null
@@ -1,7 +0,0 @@
-module inc(clock, counter);
-
-input clock;
-output reg [7:0] counter;
-always @(posedge clock)
-	counter <= counter + 1;
-endmodule	
diff --git a/tests/hana/test_simulation_always_23_test.v b/tests/hana/test_simulation_always_23_test.v
deleted file mode 100644
index f1f13bbe..00000000
--- a/tests/hana/test_simulation_always_23_test.v
+++ /dev/null
@@ -1,14 +0,0 @@
-module MyCounter (clock, preset, updown, presetdata, counter);
-input clock, preset, updown;
-input [1: 0] presetdata;
-output reg [1:0] counter;
-
-always @(posedge clock)
-    if(preset)
-	    counter <= presetdata;
-	else
-	    if(updown)
-		    counter <= counter + 1;
-		else
-		    counter <= counter - 1;
-endmodule			
diff --git a/tests/hana/test_simulation_always_27_test.v b/tests/hana/test_simulation_always_27_test.v
deleted file mode 100644
index 577378fd..00000000
--- a/tests/hana/test_simulation_always_27_test.v
+++ /dev/null
@@ -1,13 +0,0 @@
-module FlipFlop(clock, cs, ns);
-input clock;
-input cs;
-output reg ns;
-reg temp;
-
-always @(posedge clock)
-begin
-    temp <= cs;
-	ns <= temp;
-end	
-
-endmodule	
diff --git a/tests/hana/test_simulation_always_29_test.v b/tests/hana/test_simulation_always_29_test.v
deleted file mode 100644
index 55606832..00000000
--- a/tests/hana/test_simulation_always_29_test.v
+++ /dev/null
@@ -1,9 +0,0 @@
-module test(input in, output reg [1:0] out);
-
-    always @(in)
-    begin
-        out = in;
-        out = out + in;
-    end
-
-endmodule
diff --git a/tests/hana/test_simulation_always_31_tt.v b/tests/hana/test_simulation_always_31_tt.v
deleted file mode 100644
index 299c0ca4..00000000
--- a/tests/hana/test_simulation_always_31_tt.v
+++ /dev/null
@@ -1,50 +0,0 @@
-module test(clk, cond, data);
-input cond;
-input clk;
-output data;
-
-wire  synth_net;
-wire  synth_net_0;
-wire  synth_net_1;
-wire  synth_net_2;
-
-wire  synth_net_3;
-wire  synth_net_4;
-wire  synth_net_5;
-wire  synth_net_6;
-
-wire  synth_net_7;
-wire  synth_net_8;
-wire  synth_net_9;
-wire  synth_net_10;
-
-wire  synth_net_11;
-wire  tmp;
-AND2 synth_AND(.in({synth_net_0, synth_net_1}), .
-    out(synth_net_2));
-AND2 synth_AND_0(.in({synth_net_3, synth_net_4}), .out(
-    synth_net_5));
-AND2 synth_AND_1(.in({synth_net_6, synth_net_7}), .out(
-    synth_net_8));
-AND2 synth_AND_2(.in({synth_net_9, synth_net_10}), .out(
-    synth_net_11));
-BUF synth_BUF(.in(synth_net), .out(synth_net_0));
-BUF 
-    synth_BUF_0(.in(data), .out(synth_net_3));
-BUF synth_BUF_1(.in(synth_net_8)
-    , .out(tmp));
-BUF synth_BUF_2(.in(tmp), .out(synth_net_9));
-MUX2 synth_MUX(.
-    in({synth_net_2, synth_net_5}), .select(cond), .out(synth_net_6));
-MUX2 
-    synth_MUX_0(.in({synth_net_1, synth_net_4}), .select(cond), .out(synth_net_7
-    ));
-FF synth_FF(.d(synth_net_11), .clk(clk), .q(data));
-VCC synth_VCC(.out(
-    synth_net));
-VCC synth_VCC_0(.out(synth_net_1));
-VCC synth_VCC_1(.out(
-    synth_net_4));
-VCC synth_VCC_2(.out(synth_net_10));
-endmodule
-
diff --git a/tests/hana/test_simulation_and.v b/tests/hana/test_simulation_and.v
new file mode 100644
index 00000000..480e733d
--- /dev/null
+++ b/tests/hana/test_simulation_and.v
@@ -0,0 +1,35 @@
+
+// test_simulation_and_1_test.v
+module f1_test(input [1:0] in, output out);
+assign out = in[0] & in[1];
+endmodule
+
+// test_simulation_and_2_test.v
+module f2_test(input [1:0] in, output out);
+assign out = in[0] && in[1];
+endmodule
+
+// test_simulation_and_3_test.v
+module f3_test(input [2:0] in, output out);
+assign out = in[0] & in[1] & in[2];
+endmodule
+
+// test_simulation_and_4_test.v
+module f4_test(input [2:0] in, output out);
+assign out = in[0] && in[1] && in[2];
+endmodule
+
+// test_simulation_and_5_test.v
+module f5_test(input [3:0] in, output out);
+assign out = in[0] & in[1] & in[2] & in[3];
+endmodule
+
+// test_simulation_and_6_test.v
+module f6_test(input [3:0] in, output out);
+assign out = in[0] && in[1] && in[2] && in[3];
+endmodule
+
+// test_simulation_and_7_test.v
+module f7_test(input [3:0] in, output out);
+and myand(out, in[0], in[1], in[2], in[3]);
+endmodule
diff --git a/tests/hana/test_simulation_and_1_test.v b/tests/hana/test_simulation_and_1_test.v
deleted file mode 100644
index fba639ca..00000000
--- a/tests/hana/test_simulation_and_1_test.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module test(input [1:0] in, output out);
-assign out = in[0] & in[1];
-endmodule
diff --git a/tests/hana/test_simulation_and_2_test.v b/tests/hana/test_simulation_and_2_test.v
deleted file mode 100644
index 715bc7ca..00000000
--- a/tests/hana/test_simulation_and_2_test.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module test(input [1:0] in, output out);
-assign out = in[0] && in[1];
-endmodule
diff --git a/tests/hana/test_simulation_and_3_test.v b/tests/hana/test_simulation_and_3_test.v
deleted file mode 100644
index 74dccabf..00000000
--- a/tests/hana/test_simulation_and_3_test.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module test(input [2:0] in, output out);
-assign out = in[0] & in[1] & in[2];
-endmodule
diff --git a/tests/hana/test_simulation_and_4_test.v b/tests/hana/test_simulation_and_4_test.v
deleted file mode 100644
index 48ed9102..00000000
--- a/tests/hana/test_simulation_and_4_test.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module test(input [2:0] in, output out);
-assign out = in[0] && in[1] && in[2];
-endmodule
diff --git a/tests/hana/test_simulation_and_5_test.v b/tests/hana/test_simulation_and_5_test.v
deleted file mode 100644
index 29a35578..00000000
--- a/tests/hana/test_simulation_and_5_test.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module test(input [3:0] in, output out);
-assign out = in[0] & in[1] & in[2] & in[3];
-endmodule
diff --git a/tests/hana/test_simulation_and_6_test.v b/tests/hana/test_simulation_and_6_test.v
deleted file mode 100644
index ebce4eeb..00000000
--- a/tests/hana/test_simulation_and_6_test.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module test(input [3:0] in, output out);
-assign out = in[0] && in[1] && in[2] && in[3];
-endmodule
diff --git a/tests/hana/test_simulation_and_7_test.v b/tests/hana/test_simulation_and_7_test.v
deleted file mode 100644
index d394adad..00000000
--- a/tests/hana/test_simulation_and_7_test.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module test(input [3:0] in, output out);
-and myand(out, in[0], in[1], in[2], in[3]);
-endmodule
diff --git a/tests/hana/test_simulation_buffer.v b/tests/hana/test_simulation_buffer.v
new file mode 100644
index 00000000..d674b05c
--- /dev/null
+++ b/tests/hana/test_simulation_buffer.v
@@ -0,0 +1,17 @@
+
+// test_simulation_buffer_1_test.v
+module f1_test(input in, output out);
+assign out = in;
+endmodule
+
+// test_simulation_buffer_2_test.v
+module f2_test(input [1:0] in, output [1:0] out);
+assign out[0] = in[0];
+assign out[1] = in[1];
+endmodule
+
+// test_simulation_buffer_3_test.v
+module f3_test(input in, output [1:0] out);
+assign out[0] = in;
+assign out[1] = in;
+endmodule
diff --git a/tests/hana/test_simulation_buffer_1_test.v b/tests/hana/test_simulation_buffer_1_test.v
deleted file mode 100644
index e9bb7f61..00000000
--- a/tests/hana/test_simulation_buffer_1_test.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module test(input in, output out);
-assign out = in;
-endmodule
diff --git a/tests/hana/test_simulation_buffer_2_test.v b/tests/hana/test_simulation_buffer_2_test.v
deleted file mode 100644
index 9a3f5aa3..00000000
--- a/tests/hana/test_simulation_buffer_2_test.v
+++ /dev/null
@@ -1,4 +0,0 @@
-module test(input [1:0] in, output [1:0] out);
-assign out[0] = in[0];
-assign out[1] = in[1];
-endmodule
diff --git a/tests/hana/test_simulation_buffer_3_test.v b/tests/hana/test_simulation_buffer_3_test.v
deleted file mode 100644
index 9bca426d..00000000
--- a/tests/hana/test_simulation_buffer_3_test.v
+++ /dev/null
@@ -1,4 +0,0 @@
-module test(input in, output [1:0] out);
-assign out[0] = in;
-assign out[1] = in;
-endmodule
diff --git a/tests/hana/test_simulation_decoder.v b/tests/hana/test_simulation_decoder.v
new file mode 100644
index 00000000..ef9045aa
--- /dev/null
+++ b/tests/hana/test_simulation_decoder.v
@@ -0,0 +1,219 @@
+
+// test_simulation_decoder_2_test.v
+module f1_test (input [1:0] in, input enable, output reg  out);
+
+always @(in or enable)
+    if(!enable)
+	    out = 4'b0000;
+	else begin
+	   case (in)
+	       2'b00 : out = 0 ;
+	       2'b01 : out = 1;
+	       2'b10 : out = 0;
+	       2'b11 : out = 1;
+	    endcase
+	end
+endmodule
+
+// test_simulation_decoder_3_test.v
+module f2_test (input [1:0] in, input enable, output reg [2:0] out);
+
+always @(in or enable)
+    if(!enable)
+	    out = 3'b000;
+	else begin
+	   case (in)
+	       2'b00 : out = 3'b001 ;
+	       2'b01 : out = 3'b010;
+	       2'b10 : out = 3'b010;
+	       2'b11 : out = 3'b100;
+	    endcase
+	end
+endmodule
+
+// test_simulation_decoder_4_test.v
+module f3_test (input [2:0] in, output reg [7:0] out);
+
+always @(in )
+	   case (in)
+	       3'b000 : out = 8'b00000001;
+	       3'b001 : out = 8'b00000010;
+	       3'b010 : out = 8'b00000100;
+	       3'b011 : out = 8'b00001000;
+	       3'b100 : out = 8'b00010000;
+	       3'b101 : out = 8'b00100000;
+	       3'b110 : out = 8'b01000000;
+	       3'b111 : out = 8'b10000000;
+	    endcase
+endmodule	
+
+// test_simulation_decoder_5_test.v
+module f4_test (input [2:0] in, input enable, output reg [7:0] out);
+
+always @(in or enable )
+    if(!enable)
+	    out = 8'b00000000;
+	else	
+	   case (in)
+	       3'b000 : out = 8'b00000001;
+	       3'b001 : out = 8'b00000010;
+	       3'b010 : out = 8'b00000100;
+	       3'b011 : out = 8'b00001000;
+	       3'b100 : out = 8'b00010000;
+	       3'b101 : out = 8'b00100000;
+	       3'b110 : out = 8'b01000000;
+	       3'b111 : out = 8'b10000000;
+	    endcase
+endmodule	
+
+// test_simulation_decoder_6_test.v
+module f5_test (input [3:0] in, input enable, output reg [15:0] out);
+
+always @(in or enable)
+    if(!enable)
+	    out = 16'b0000000000000000;
+	else begin
+	   case (in)
+	       4'b0000 : out = 16'b0000000000000001;
+	       4'b0001 : out = 16'b0000000000000010;
+	       4'b0010 : out = 16'b0000000000000100;
+	       4'b0011 : out = 16'b0000000000001000;
+	       4'b0100 : out = 16'b0000000000010000;
+	       4'b0101 : out = 16'b0000000000100000;
+	       4'b0110 : out = 16'b0000000001000000;
+	       4'b0111 : out = 16'b0000000010000000;
+	       4'b1000 : out = 16'b0000000100000000;
+	       4'b1001 : out = 16'b0000001000000000;
+	       4'b1010 : out = 16'b0000010000000000;
+	       4'b1011 : out = 16'b0000100000000000;
+	       4'b1100 : out = 16'b0001000000000000;
+	       4'b1101 : out = 16'b0010000000000000;
+	       4'b1110 : out = 16'b0100000000000000;
+	       4'b1111 : out = 16'b1000000000000000;
+	    endcase
+	end
+endmodule	
+
+
+// test_simulation_decoder_7_test.v
+module f6_test (input [4:0] in, input enable, output reg [31:0] out);
+
+always @(in or enable)
+    if(!enable)
+	    out = 32'b00000000000000000000000000000000;
+	else begin
+	   case (in)
+	       5'b00000 : out = 32'b00000000000000000000000000000001;
+	       5'b00001 : out = 32'b00000000000000000000000000000010;
+	       5'b00010 : out = 32'b00000000000000000000000000000100;
+	       5'b00011 : out = 32'b00000000000000000000000000001000;
+	       5'b00100 : out = 32'b00000000000000000000000000010000;
+	       5'b00101 : out = 32'b00000000000000000000000000100000;
+	       5'b00110 : out = 32'b00000000000000000000000001000000;
+	       5'b00111 : out = 32'b00000000000000000000000010000000;
+	       5'b01000 : out = 32'b00000000000000000000000100000000;
+	       5'b01001 : out = 32'b00000000000000000000001000000000;
+	       5'b01010 : out = 32'b00000000000000000000010000000000;
+	       5'b01011 : out = 32'b00000000000000000000100000000000;
+	       5'b01100 : out = 32'b00000000000000000001000000000000;
+	       5'b01101 : out = 32'b00000000000000000010000000000000;
+	       5'b01110 : out = 32'b00000000000000000100000000000000;
+	       5'b01111 : out = 32'b00000000000000001000000000000000;
+	       5'b10000 : out = 32'b00000000000000010000000000000000;
+	       5'b10001 : out = 32'b00000000000000100000000000000000;
+	       5'b10010 : out = 32'b00000000000001000000000000000000;
+	       5'b10011 : out = 32'b00000000000010000000000000000000;
+	       5'b10100 : out = 32'b00000000000100000000000000000000;
+	       5'b10101 : out = 32'b00000000001000000000000000000000;
+	       5'b10110 : out = 32'b00000000010000000000000000000000;
+	       5'b10111 : out = 32'b00000000100000000000000000000000;
+	       5'b11000 : out = 32'b00000001000000000000000000000000;
+	       5'b11001 : out = 32'b00000010000000000000000000000000;
+	       5'b11010 : out = 32'b00000100000000000000000000000000;
+	       5'b11011 : out = 32'b00001000000000000000000000000000;
+	       5'b11100 : out = 32'b00010000000000000000000000000000;
+	       5'b11101 : out = 32'b00100000000000000000000000000000;
+	       5'b11110 : out = 32'b01000000000000000000000000000000;
+	       5'b11111 : out = 32'b10000000000000000000000000000000;
+	    endcase
+	end
+endmodule	
+
+
+// test_simulation_decoder_8_test.v
+module f7_test (input [5:0] in, input enable, output reg [63:0] out);
+
+always @(in or enable)
+    if(!enable)
+	    out = 64'b0000000000000000000000000000000000000000000000000000000000000000;
+	else begin
+	   case (in)
+	       6'b000000 : out = 64'b0000000000000000000000000000000000000000000000000000000000000001;
+	       6'b000001 : out = 64'b0000000000000000000000000000000000000000000000000000000000000010;
+	       6'b000010 : out = 64'b0000000000000000000000000000000000000000000000000000000000000100;
+	       6'b000011 : out = 64'b0000000000000000000000000000000000000000000000000000000000001000;
+	       6'b000100 : out = 64'b0000000000000000000000000000000000000000000000000000000000010000;
+	       6'b000101 : out = 64'b0000000000000000000000000000000000000000000000000000000000100000;
+	       6'b000110 : out = 64'b0000000000000000000000000000000000000000000000000000000001000000;
+	       6'b000111 : out = 64'b0000000000000000000000000000000000000000000000000000000010000000;
+	       6'b001000 : out = 64'b0000000000000000000000000000000000000000000000000000000100000000;
+	       6'b001001 : out = 64'b0000000000000000000000000000000000000000000000000000001000000000;
+	       6'b001010 : out = 64'b0000000000000000000000000000000000000000000000000000010000000000;
+	       6'b001011 : out = 64'b0000000000000000000000000000000000000000000000000000100000000000;
+	       6'b001100 : out = 64'b0000000000000000000000000000000000000000000000000001000000000000;
+	       6'b001101 : out = 64'b0000000000000000000000000000000000000000000000000010000000000000;
+	       6'b001110 : out = 64'b0000000000000000000000000000000000000000000000000100000000000000;
+	       6'b001111 : out = 64'b0000000000000000000000000000000000000000000000001000000000000000;
+	       6'b010000 : out = 64'b0000000000000000000000000000000000000000000000010000000000000000;
+	       6'b010001 : out = 64'b0000000000000000000000000000000000000000000000100000000000000000;
+	       6'b010010 : out = 64'b0000000000000000000000000000000000000000000001000000000000000000;
+	       6'b010011 : out = 64'b0000000000000000000000000000000000000000000010000000000000000000;
+	       6'b010100 : out = 64'b0000000000000000000000000000000000000000000100000000000000000000;
+	       6'b010101 : out = 64'b0000000000000000000000000000000000000000001000000000000000000000;
+	       6'b010110 : out = 64'b0000000000000000000000000000000000000000010000000000000000000000;
+	       6'b010111 : out = 64'b0000000000000000000000000000000000000000100000000000000000000000;
+	       6'b011000 : out = 64'b0000000000000000000000000000000000000001000000000000000000000000;
+	       6'b011001 : out = 64'b0000000000000000000000000000000000000010000000000000000000000000;
+	       6'b011010 : out = 64'b0000000000000000000000000000000000000100000000000000000000000000;
+	       6'b011011 : out = 64'b0000000000000000000000000000000000001000000000000000000000000000;
+	       6'b011100 : out = 64'b0000000000000000000000000000000000010000000000000000000000000000;
+	       6'b011101 : out = 64'b0000000000000000000000000000000000100000000000000000000000000000;
+	       6'b011110 : out = 64'b0000000000000000000000000000000001000000000000000000000000000000;
+	       6'b011111 : out = 64'b0000000000000000000000000000000010000000000000000000000000000000;
+
+	       6'b100000 : out = 64'b0000000000000000000000000000000100000000000000000000000000000000;
+	       6'b100001 : out = 64'b0000000000000000000000000000001000000000000000000000000000000000;
+	       6'b100010 : out = 64'b0000000000000000000000000000010000000000000000000000000000000000;
+	       6'b100011 : out = 64'b0000000000000000000000000000100000000000000000000000000000000000;
+	       6'b100100 : out = 64'b0000000000000000000000000001000000000000000000000000000000000000;
+	       6'b100101 : out = 64'b0000000000000000000000000010000000000000000000000000000000000000;
+	       6'b100110 : out = 64'b0000000000000000000000000100000000000000000000000000000000000000;
+	       6'b100111 : out = 64'b0000000000000000000000001000000000000000000000000000000000000000;
+	       6'b101000 : out = 64'b0000000000000000000000010000000000000000000000000000000000000000;
+	       6'b101001 : out = 64'b0000000000000000000000100000000000000000000000000000000000000000;
+	       6'b101010 : out = 64'b0000000000000000000001000000000000000000000000000000000000000000;
+	       6'b101011 : out = 64'b0000000000000000000010000000000000000000000000000000000000000000;
+	       6'b101100 : out = 64'b0000000000000000000100000000000000000000000000000000000000000000;
+	       6'b101101 : out = 64'b0000000000000000001000000000000000000000000000000000000000000000;
+	       6'b101110 : out = 64'b0000000000000000010000000000000000000000000000000000000000000000;
+	       6'b101111 : out = 64'b0000000000000000100000000000000000000000000000000000000000000000;
+	       6'b110000 : out = 64'b0000000000000001000000000000000000000000000000000000000000000000;
+	       6'b110001 : out = 64'b0000000000000010000000000000000000000000000000000000000000000000;
+	       6'b110010 : out = 64'b0000000000000100000000000000000000000000000000000000000000000000;
+	       6'b110011 : out = 64'b0000000000001000000000000000000000000000000000000000000000000000;
+	       6'b110100 : out = 64'b0000000000010000000000000000000000000000000000000000000000000000;
+	       6'b110101 : out = 64'b0000000000100000000000000000000000000000000000000000000000000000;
+	       6'b110110 : out = 64'b0000000001000000000000000000000000000000000000000000000000000000;
+	       6'b110111 : out = 64'b0000000010000000000000000000000000000000000000000000000000000000;
+	       6'b111000 : out = 64'b0000000100000000000000000000000000000000000000000000000000000000;
+	       6'b111001 : out = 64'b0000001000000000000000000000000000000000000000000000000000000000;
+	       6'b111010 : out = 64'b0000010000000000000000000000000000000000000000000000000000000000;
+	       6'b111011 : out = 64'b0000100000000000000000000000000000000000000000000000000000000000;
+	       6'b111100 : out = 64'b0001000000000000000000000000000000000000000000000000000000000000;
+	       6'b111101 : out = 64'b0010000000000000000000000000000000000000000000000000000000000000;
+	       6'b111110 : out = 64'b0100000000000000000000000000000000000000000000000000000000000000;
+	       6'b111111 : out = 64'b1000000000000000000000000000000000000000000000000000000000000000;
+	    endcase
+	end
+endmodule	
+
diff --git a/tests/hana/test_simulation_decoder_2_test.v b/tests/hana/test_simulation_decoder_2_test.v
deleted file mode 100644
index 5bdf1971..00000000
--- a/tests/hana/test_simulation_decoder_2_test.v
+++ /dev/null
@@ -1,14 +0,0 @@
-module test (input [1:0] in, input enable, output reg  out);
-
-always @(in or enable)
-    if(!enable)
-	    out = 4'b0000;
-	else begin
-	   case (in)
-	       2'b00 : out = 0 ;
-	       2'b01 : out = 1;
-	       2'b10 : out = 0;
-	       2'b11 : out = 1;
-	    endcase
-	end
-endmodule
diff --git a/tests/hana/test_simulation_decoder_3_test.v b/tests/hana/test_simulation_decoder_3_test.v
deleted file mode 100644
index 44f5de12..00000000
--- a/tests/hana/test_simulation_decoder_3_test.v
+++ /dev/null
@@ -1,14 +0,0 @@
-module test (input [1:0] in, input enable, output reg [2:0] out);
-
-always @(in or enable)
-    if(!enable)
-	    out = 3'b000;
-	else begin
-	   case (in)
-	       2'b00 : out = 3'b001 ;
-	       2'b01 : out = 3'b010;
-	       2'b10 : out = 3'b010;
-	       2'b11 : out = 3'b100;
-	    endcase
-	end
-endmodule
diff --git a/tests/hana/test_simulation_decoder_4_test.v b/tests/hana/test_simulation_decoder_4_test.v
deleted file mode 100644
index 871a5bbf..00000000
--- a/tests/hana/test_simulation_decoder_4_test.v
+++ /dev/null
@@ -1,14 +0,0 @@
-module test (input [2:0] in, output reg [7:0] out);
-
-always @(in )
-	   case (in)
-	       3'b000 : out = 8'b00000001;
-	       3'b001 : out = 8'b00000010;
-	       3'b010 : out = 8'b00000100;
-	       3'b011 : out = 8'b00001000;
-	       3'b100 : out = 8'b00010000;
-	       3'b101 : out = 8'b00100000;
-	       3'b110 : out = 8'b01000000;
-	       3'b111 : out = 8'b10000000;
-	    endcase
-endmodule	
diff --git a/tests/hana/test_simulation_decoder_5_test.v b/tests/hana/test_simulation_decoder_5_test.v
deleted file mode 100644
index 497fa4bf..00000000
--- a/tests/hana/test_simulation_decoder_5_test.v
+++ /dev/null
@@ -1,17 +0,0 @@
-module test (input [2:0] in, input enable, output reg [7:0] out);
-
-always @(in or enable )
-    if(!enable)
-	    out = 8'b00000000;
-	else	
-	   case (in)
-	       3'b000 : out = 8'b00000001;
-	       3'b001 : out = 8'b00000010;
-	       3'b010 : out = 8'b00000100;
-	       3'b011 : out = 8'b00001000;
-	       3'b100 : out = 8'b00010000;
-	       3'b101 : out = 8'b00100000;
-	       3'b110 : out = 8'b01000000;
-	       3'b111 : out = 8'b10000000;
-	    endcase
-endmodule	
diff --git a/tests/hana/test_simulation_decoder_6_test.v b/tests/hana/test_simulation_decoder_6_test.v
deleted file mode 100644
index fd19ad60..00000000
--- a/tests/hana/test_simulation_decoder_6_test.v
+++ /dev/null
@@ -1,27 +0,0 @@
-module test (input [3:0] in, input enable, output reg [15:0] out);
-
-always @(in or enable)
-    if(!enable)
-	    out = 16'b0000000000000000;
-	else begin
-	   case (in)
-	       4'b0000 : out = 16'b0000000000000001;
-	       4'b0001 : out = 16'b0000000000000010;
-	       4'b0010 : out = 16'b0000000000000100;
-	       4'b0011 : out = 16'b0000000000001000;
-	       4'b0100 : out = 16'b0000000000010000;
-	       4'b0101 : out = 16'b0000000000100000;
-	       4'b0110 : out = 16'b0000000001000000;
-	       4'b0111 : out = 16'b0000000010000000;
-	       4'b1000 : out = 16'b0000000100000000;
-	       4'b1001 : out = 16'b0000001000000000;
-	       4'b1010 : out = 16'b0000010000000000;
-	       4'b1011 : out = 16'b0000100000000000;
-	       4'b1100 : out = 16'b0001000000000000;
-	       4'b1101 : out = 16'b0010000000000000;
-	       4'b1110 : out = 16'b0100000000000000;
-	       4'b1111 : out = 16'b1000000000000000;
-	    endcase
-	end
-endmodule	
-
diff --git a/tests/hana/test_simulation_decoder_7_test.v b/tests/hana/test_simulation_decoder_7_test.v
deleted file mode 100644
index 462e9419..00000000
--- a/tests/hana/test_simulation_decoder_7_test.v
+++ /dev/null
@@ -1,43 +0,0 @@
-module test (input [4:0] in, input enable, output reg [31:0] out);
-
-always @(in or enable)
-    if(!enable)
-	    out = 32'b00000000000000000000000000000000;
-	else begin
-	   case (in)
-	       5'b00000 : out = 32'b00000000000000000000000000000001;
-	       5'b00001 : out = 32'b00000000000000000000000000000010;
-	       5'b00010 : out = 32'b00000000000000000000000000000100;
-	       5'b00011 : out = 32'b00000000000000000000000000001000;
-	       5'b00100 : out = 32'b00000000000000000000000000010000;
-	       5'b00101 : out = 32'b00000000000000000000000000100000;
-	       5'b00110 : out = 32'b00000000000000000000000001000000;
-	       5'b00111 : out = 32'b00000000000000000000000010000000;
-	       5'b01000 : out = 32'b00000000000000000000000100000000;
-	       5'b01001 : out = 32'b00000000000000000000001000000000;
-	       5'b01010 : out = 32'b00000000000000000000010000000000;
-	       5'b01011 : out = 32'b00000000000000000000100000000000;
-	       5'b01100 : out = 32'b00000000000000000001000000000000;
-	       5'b01101 : out = 32'b00000000000000000010000000000000;
-	       5'b01110 : out = 32'b00000000000000000100000000000000;
-	       5'b01111 : out = 32'b00000000000000001000000000000000;
-	       5'b10000 : out = 32'b00000000000000010000000000000000;
-	       5'b10001 : out = 32'b00000000000000100000000000000000;
-	       5'b10010 : out = 32'b00000000000001000000000000000000;
-	       5'b10011 : out = 32'b00000000000010000000000000000000;
-	       5'b10100 : out = 32'b00000000000100000000000000000000;
-	       5'b10101 : out = 32'b00000000001000000000000000000000;
-	       5'b10110 : out = 32'b00000000010000000000000000000000;
-	       5'b10111 : out = 32'b00000000100000000000000000000000;
-	       5'b11000 : out = 32'b00000001000000000000000000000000;
-	       5'b11001 : out = 32'b00000010000000000000000000000000;
-	       5'b11010 : out = 32'b00000100000000000000000000000000;
-	       5'b11011 : out = 32'b00001000000000000000000000000000;
-	       5'b11100 : out = 32'b00010000000000000000000000000000;
-	       5'b11101 : out = 32'b00100000000000000000000000000000;
-	       5'b11110 : out = 32'b01000000000000000000000000000000;
-	       5'b11111 : out = 32'b10000000000000000000000000000000;
-	    endcase
-	end
-endmodule	
-
diff --git a/tests/hana/test_simulation_decoder_8_test.v b/tests/hana/test_simulation_decoder_8_test.v
deleted file mode 100644
index 751d60f6..00000000
--- a/tests/hana/test_simulation_decoder_8_test.v
+++ /dev/null
@@ -1,76 +0,0 @@
-module test (input [5:0] in, input enable, output reg [63:0] out);
-
-always @(in or enable)
-    if(!enable)
-	    out = 64'b0000000000000000000000000000000000000000000000000000000000000000;
-	else begin
-	   case (in)
-	       6'b000000 : out = 64'b0000000000000000000000000000000000000000000000000000000000000001;
-	       6'b000001 : out = 64'b0000000000000000000000000000000000000000000000000000000000000010;
-	       6'b000010 : out = 64'b0000000000000000000000000000000000000000000000000000000000000100;
-	       6'b000011 : out = 64'b0000000000000000000000000000000000000000000000000000000000001000;
-	       6'b000100 : out = 64'b0000000000000000000000000000000000000000000000000000000000010000;
-	       6'b000101 : out = 64'b0000000000000000000000000000000000000000000000000000000000100000;
-	       6'b000110 : out = 64'b0000000000000000000000000000000000000000000000000000000001000000;
-	       6'b000111 : out = 64'b0000000000000000000000000000000000000000000000000000000010000000;
-	       6'b001000 : out = 64'b0000000000000000000000000000000000000000000000000000000100000000;
-	       6'b001001 : out = 64'b0000000000000000000000000000000000000000000000000000001000000000;
-	       6'b001010 : out = 64'b0000000000000000000000000000000000000000000000000000010000000000;
-	       6'b001011 : out = 64'b0000000000000000000000000000000000000000000000000000100000000000;
-	       6'b001100 : out = 64'b0000000000000000000000000000000000000000000000000001000000000000;
-	       6'b001101 : out = 64'b0000000000000000000000000000000000000000000000000010000000000000;
-	       6'b001110 : out = 64'b0000000000000000000000000000000000000000000000000100000000000000;
-	       6'b001111 : out = 64'b0000000000000000000000000000000000000000000000001000000000000000;
-	       6'b010000 : out = 64'b0000000000000000000000000000000000000000000000010000000000000000;
-	       6'b010001 : out = 64'b0000000000000000000000000000000000000000000000100000000000000000;
-	       6'b010010 : out = 64'b0000000000000000000000000000000000000000000001000000000000000000;
-	       6'b010011 : out = 64'b0000000000000000000000000000000000000000000010000000000000000000;
-	       6'b010100 : out = 64'b0000000000000000000000000000000000000000000100000000000000000000;
-	       6'b010101 : out = 64'b0000000000000000000000000000000000000000001000000000000000000000;
-	       6'b010110 : out = 64'b0000000000000000000000000000000000000000010000000000000000000000;
-	       6'b010111 : out = 64'b0000000000000000000000000000000000000000100000000000000000000000;
-	       6'b011000 : out = 64'b0000000000000000000000000000000000000001000000000000000000000000;
-	       6'b011001 : out = 64'b0000000000000000000000000000000000000010000000000000000000000000;
-	       6'b011010 : out = 64'b0000000000000000000000000000000000000100000000000000000000000000;
-	       6'b011011 : out = 64'b0000000000000000000000000000000000001000000000000000000000000000;
-	       6'b011100 : out = 64'b0000000000000000000000000000000000010000000000000000000000000000;
-	       6'b011101 : out = 64'b0000000000000000000000000000000000100000000000000000000000000000;
-	       6'b011110 : out = 64'b0000000000000000000000000000000001000000000000000000000000000000;
-	       6'b011111 : out = 64'b0000000000000000000000000000000010000000000000000000000000000000;
-
-	       6'b100000 : out = 64'b0000000000000000000000000000000100000000000000000000000000000000;
-	       6'b100001 : out = 64'b0000000000000000000000000000001000000000000000000000000000000000;
-	       6'b100010 : out = 64'b0000000000000000000000000000010000000000000000000000000000000000;
-	       6'b100011 : out = 64'b0000000000000000000000000000100000000000000000000000000000000000;
-	       6'b100100 : out = 64'b0000000000000000000000000001000000000000000000000000000000000000;
-	       6'b100101 : out = 64'b0000000000000000000000000010000000000000000000000000000000000000;
-	       6'b100110 : out = 64'b0000000000000000000000000100000000000000000000000000000000000000;
-	       6'b100111 : out = 64'b0000000000000000000000001000000000000000000000000000000000000000;
-	       6'b101000 : out = 64'b0000000000000000000000010000000000000000000000000000000000000000;
-	       6'b101001 : out = 64'b0000000000000000000000100000000000000000000000000000000000000000;
-	       6'b101010 : out = 64'b0000000000000000000001000000000000000000000000000000000000000000;
-	       6'b101011 : out = 64'b0000000000000000000010000000000000000000000000000000000000000000;
-	       6'b101100 : out = 64'b0000000000000000000100000000000000000000000000000000000000000000;
-	       6'b101101 : out = 64'b0000000000000000001000000000000000000000000000000000000000000000;
-	       6'b101110 : out = 64'b0000000000000000010000000000000000000000000000000000000000000000;
-	       6'b101111 : out = 64'b0000000000000000100000000000000000000000000000000000000000000000;
-	       6'b110000 : out = 64'b0000000000000001000000000000000000000000000000000000000000000000;
-	       6'b110001 : out = 64'b0000000000000010000000000000000000000000000000000000000000000000;
-	       6'b110010 : out = 64'b0000000000000100000000000000000000000000000000000000000000000000;
-	       6'b110011 : out = 64'b0000000000001000000000000000000000000000000000000000000000000000;
-	       6'b110100 : out = 64'b0000000000010000000000000000000000000000000000000000000000000000;
-	       6'b110101 : out = 64'b0000000000100000000000000000000000000000000000000000000000000000;
-	       6'b110110 : out = 64'b0000000001000000000000000000000000000000000000000000000000000000;
-	       6'b110111 : out = 64'b0000000010000000000000000000000000000000000000000000000000000000;
-	       6'b111000 : out = 64'b0000000100000000000000000000000000000000000000000000000000000000;
-	       6'b111001 : out = 64'b0000001000000000000000000000000000000000000000000000000000000000;
-	       6'b111010 : out = 64'b0000010000000000000000000000000000000000000000000000000000000000;
-	       6'b111011 : out = 64'b0000100000000000000000000000000000000000000000000000000000000000;
-	       6'b111100 : out = 64'b0001000000000000000000000000000000000000000000000000000000000000;
-	       6'b111101 : out = 64'b0010000000000000000000000000000000000000000000000000000000000000;
-	       6'b111110 : out = 64'b0100000000000000000000000000000000000000000000000000000000000000;
-	       6'b111111 : out = 64'b1000000000000000000000000000000000000000000000000000000000000000;
-	    endcase
-	end
-endmodule	
-
diff --git a/tests/hana/test_simulation_inc.v b/tests/hana/test_simulation_inc.v
new file mode 100644
index 00000000..f8f54870
--- /dev/null
+++ b/tests/hana/test_simulation_inc.v
@@ -0,0 +1,42 @@
+
+// test_simulation_inc_16_test.v
+module f1_test(input [15:0] in, output [15:0] out);
+
+assign out = -in;
+
+endmodule
+
+// test_simulation_inc_1_test.v
+module f2_test(input in, output  out);
+
+assign out = -in;
+
+endmodule
+
+// test_simulation_inc_2_test.v
+module f3_test(input [1:0] in, output [1:0] out);
+
+assign out = -in;
+
+endmodule
+
+// test_simulation_inc_32_test.v
+module f4_test(input [31:0] in, output [31:0] out);
+
+assign out = -in;
+
+endmodule
+
+// test_simulation_inc_4_test.v
+module f5_test(input [3:0] in, output [3:0] out);
+
+assign out = -in;
+
+endmodule
+
+// test_simulation_inc_8_test.v
+module f6_test(input [7:0] in, output [7:0] out);
+
+assign out = -in;
+
+endmodule
diff --git a/tests/hana/test_simulation_inc_16_test.v b/tests/hana/test_simulation_inc_16_test.v
deleted file mode 100644
index 7ff42ff5..00000000
--- a/tests/hana/test_simulation_inc_16_test.v
+++ /dev/null
@@ -1,5 +0,0 @@
-module test(input [15:0] in, output [15:0] out);
-
-assign out = -in;
-
-endmodule
diff --git a/tests/hana/test_simulation_inc_1_test.v b/tests/hana/test_simulation_inc_1_test.v
deleted file mode 100644
index 02bec2c2..00000000
--- a/tests/hana/test_simulation_inc_1_test.v
+++ /dev/null
@@ -1,5 +0,0 @@
-module test(input in, output  out);
-
-assign out = -in;
-
-endmodule
diff --git a/tests/hana/test_simulation_inc_2_test.v b/tests/hana/test_simulation_inc_2_test.v
deleted file mode 100644
index b96e05a2..00000000
--- a/tests/hana/test_simulation_inc_2_test.v
+++ /dev/null
@@ -1,5 +0,0 @@
-module test(input [1:0] in, output [1:0] out);
-
-assign out = -in;
-
-endmodule
diff --git a/tests/hana/test_simulation_inc_32_test.v b/tests/hana/test_simulation_inc_32_test.v
deleted file mode 100644
index 5700d0ce..00000000
--- a/tests/hana/test_simulation_inc_32_test.v
+++ /dev/null
@@ -1,5 +0,0 @@
-module test(input [31:0] in, output [31:0] out);
-
-assign out = -in;
-
-endmodule
diff --git a/tests/hana/test_simulation_inc_4_test.v b/tests/hana/test_simulation_inc_4_test.v
deleted file mode 100644
index 34940d63..00000000
--- a/tests/hana/test_simulation_inc_4_test.v
+++ /dev/null
@@ -1,5 +0,0 @@
-module test(input [3:0] in, output [3:0] out);
-
-assign out = -in;
-
-endmodule
diff --git a/tests/hana/test_simulation_inc_8_test.v b/tests/hana/test_simulation_inc_8_test.v
deleted file mode 100644
index c36d69f0..00000000
--- a/tests/hana/test_simulation_inc_8_test.v
+++ /dev/null
@@ -1,5 +0,0 @@
-module test(input [7:0] in, output [7:0] out);
-
-assign out = -in;
-
-endmodule
diff --git a/tests/hana/test_simulation_mod_1_xx.v b/tests/hana/test_simulation_mod_1_xx.v
deleted file mode 100644
index 75144a8e..00000000
--- a/tests/hana/test_simulation_mod_1_xx.v
+++ /dev/null
@@ -1,13 +0,0 @@
-module test(in1, in2, out);
-input in1;
-input in2;
-output out;
-
-wire  synth_net_0;
-wire  synth_net_1;
-BUF synth_BUF_0(.in(synth_net_1), .out(out
-    ));
-DIV1 synth_DIV(.in1(in1), .in2(in2), .rem(synth_net_0), .out(synth_net_1
-    ));
-endmodule
-
diff --git a/tests/hana/test_simulation_mux.v b/tests/hana/test_simulation_mux.v
new file mode 100644
index 00000000..085387ef
--- /dev/null
+++ b/tests/hana/test_simulation_mux.v
@@ -0,0 +1,176 @@
+
+// test_simulation_mux_16_test.v
+module f1_test(input [15:0] in, input [3:0] select, output reg out);
+
+always @( in or select)
+    case (select)
+	    0: out = in[0];
+	    1: out = in[1];
+	    2: out = in[2];
+	    3: out = in[3];
+	    4: out = in[4];
+	    5: out = in[5];
+	    6: out = in[6];
+	    7: out = in[7];
+	    8: out = in[8];
+	    9: out = in[9];
+	    10: out = in[10];
+	    11: out = in[11];
+	    12: out = in[12];
+	    13: out = in[13];
+	    14: out = in[14];
+	    15: out = in[15];
+	endcase
+endmodule
+
+// test_simulation_mux_2_test.v
+module f2_test(input [1:0] in, input select, output reg out);
+
+always @( in or select)
+    case (select)
+	    0: out = in[0];
+	    1: out = in[1];
+	endcase
+endmodule	
+
+// test_simulation_mux_32_test.v
+module f3_test(input [31:0] in, input [4:0] select, output reg out);
+
+always @( in or select)
+    case (select)
+	    0: out = in[0];
+	    1: out = in[1];
+	    2: out = in[2];
+	    3: out = in[3];
+	    4: out = in[4];
+	    5: out = in[5];
+	    6: out = in[6];
+	    7: out = in[7];
+	    8: out = in[8];
+	    9: out = in[9];
+	    10: out = in[10];
+	    11: out = in[11];
+	    12: out = in[12];
+	    13: out = in[13];
+	    14: out = in[14];
+	    15: out = in[15];
+	    16: out = in[16];
+	    17: out = in[17];
+	    18: out = in[18];
+	    19: out = in[19];
+	    20: out = in[20];
+	    21: out = in[21];
+	    22: out = in[22];
+	    23: out = in[23];
+	    24: out = in[24];
+	    25: out = in[25];
+	    26: out = in[26];
+	    27: out = in[27];
+	    28: out = in[28];
+	    29: out = in[29];
+	    30: out = in[30];
+	    31: out = in[31];
+	endcase
+endmodule	
+
+
+// test_simulation_mux_4_test.v
+module f4_test(input [3:0] in, input [1:0] select, output reg out);
+
+always @( in or select)
+    case (select)
+	    0: out = in[0];
+	    1: out = in[1];
+	    2: out = in[2];
+	    3: out = in[3];
+	endcase
+endmodule	
+
+// test_simulation_mux_64_test.v
+module f5_test(input [63:0] in, input [5:0] select, output reg out);
+
+always @( in or select)
+    case (select)
+	    0: out = in[0];
+	    1: out = in[1];
+	    2: out = in[2];
+	    3: out = in[3];
+	    4: out = in[4];
+	    5: out = in[5];
+	    6: out = in[6];
+	    7: out = in[7];
+	    8: out = in[8];
+	    9: out = in[9];
+	    10: out = in[10];
+	    11: out = in[11];
+	    12: out = in[12];
+	    13: out = in[13];
+	    14: out = in[14];
+	    15: out = in[15];
+	    16: out = in[16];
+	    17: out = in[17];
+	    18: out = in[18];
+	    19: out = in[19];
+	    20: out = in[20];
+	    21: out = in[21];
+	    22: out = in[22];
+	    23: out = in[23];
+	    24: out = in[24];
+	    25: out = in[25];
+	    26: out = in[26];
+	    27: out = in[27];
+	    28: out = in[28];
+	    29: out = in[29];
+	    30: out = in[30];
+	    31: out = in[31];
+	    32: out = in[32];
+	    33: out = in[33];
+	    34: out = in[34];
+	    35: out = in[35];
+	    36: out = in[36];
+	    37: out = in[37];
+	    38: out = in[38];
+	    39: out = in[39];
+	    40: out = in[40];
+	    41: out = in[41];
+	    42: out = in[42];
+	    43: out = in[43];
+	    44: out = in[44];
+	    45: out = in[45];
+	    46: out = in[46];
+	    47: out = in[47];
+	    48: out = in[48];
+	    49: out = in[49];
+	    50: out = in[50];
+	    51: out = in[51];
+	    52: out = in[52];
+	    53: out = in[53];
+	    54: out = in[54];
+	    55: out = in[55];
+	    56: out = in[56];
+	    57: out = in[57];
+	    58: out = in[58];
+	    59: out = in[59];
+	    60: out = in[60];
+	    61: out = in[61];
+	    62: out = in[62];
+	    63: out = in[63];
+	endcase
+endmodule	
+
+
+// test_simulation_mux_8_test.v
+module f6_test(input [7:0] in, input [2:0] select, output reg out);
+
+always @( in or select)
+    case (select)
+	    0: out = in[0];
+	    1: out = in[1];
+	    2: out = in[2];
+	    3: out = in[3];
+	    4: out = in[4];
+	    5: out = in[5];
+	    6: out = in[6];
+	    7: out = in[7];
+	endcase
+endmodule
diff --git a/tests/hana/test_simulation_mux_16_test.v b/tests/hana/test_simulation_mux_16_test.v
deleted file mode 100644
index de4b6f8e..00000000
--- a/tests/hana/test_simulation_mux_16_test.v
+++ /dev/null
@@ -1,22 +0,0 @@
-module test(input [15:0] in, input [3:0] select, output reg out);
-
-always @( in or select)
-    case (select)
-	    0: out = in[0];
-	    1: out = in[1];
-	    2: out = in[2];
-	    3: out = in[3];
-	    4: out = in[4];
-	    5: out = in[5];
-	    6: out = in[6];
-	    7: out = in[7];
-	    8: out = in[8];
-	    9: out = in[9];
-	    10: out = in[10];
-	    11: out = in[11];
-	    12: out = in[12];
-	    13: out = in[13];
-	    14: out = in[14];
-	    15: out = in[15];
-	endcase
-endmodule
diff --git a/tests/hana/test_simulation_mux_2_test.v b/tests/hana/test_simulation_mux_2_test.v
deleted file mode 100644
index bc676c70..00000000
--- a/tests/hana/test_simulation_mux_2_test.v
+++ /dev/null
@@ -1,8 +0,0 @@
-module test(input [1:0] in, input select, output reg out);
-
-always @( in or select)
-    case (select)
-	    0: out = in[0];
-	    1: out = in[1];
-	endcase
-endmodule	
diff --git a/tests/hana/test_simulation_mux_32_test.v b/tests/hana/test_simulation_mux_32_test.v
deleted file mode 100644
index 16de4d7f..00000000
--- a/tests/hana/test_simulation_mux_32_test.v
+++ /dev/null
@@ -1,39 +0,0 @@
-module test(input [31:0] in, input [4:0] select, output reg out);
-
-always @( in or select)
-    case (select)
-	    0: out = in[0];
-	    1: out = in[1];
-	    2: out = in[2];
-	    3: out = in[3];
-	    4: out = in[4];
-	    5: out = in[5];
-	    6: out = in[6];
-	    7: out = in[7];
-	    8: out = in[8];
-	    9: out = in[9];
-	    10: out = in[10];
-	    11: out = in[11];
-	    12: out = in[12];
-	    13: out = in[13];
-	    14: out = in[14];
-	    15: out = in[15];
-	    16: out = in[16];
-	    17: out = in[17];
-	    18: out = in[18];
-	    19: out = in[19];
-	    20: out = in[20];
-	    21: out = in[21];
-	    22: out = in[22];
-	    23: out = in[23];
-	    24: out = in[24];
-	    25: out = in[25];
-	    26: out = in[26];
-	    27: out = in[27];
-	    28: out = in[28];
-	    29: out = in[29];
-	    30: out = in[30];
-	    31: out = in[31];
-	endcase
-endmodule	
-
diff --git a/tests/hana/test_simulation_mux_4_test.v b/tests/hana/test_simulation_mux_4_test.v
deleted file mode 100644
index 6a112c6a..00000000
--- a/tests/hana/test_simulation_mux_4_test.v
+++ /dev/null
@@ -1,10 +0,0 @@
-module test(input [3:0] in, input [1:0] select, output reg out);
-
-always @( in or select)
-    case (select)
-	    0: out = in[0];
-	    1: out = in[1];
-	    2: out = in[2];
-	    3: out = in[3];
-	endcase
-endmodule	
diff --git a/tests/hana/test_simulation_mux_64_test.v b/tests/hana/test_simulation_mux_64_test.v
deleted file mode 100644
index 420239c6..00000000
--- a/tests/hana/test_simulation_mux_64_test.v
+++ /dev/null
@@ -1,71 +0,0 @@
-module test(input [63:0] in, input [5:0] select, output reg out);
-
-always @( in or select)
-    case (select)
-	    0: out = in[0];
-	    1: out = in[1];
-	    2: out = in[2];
-	    3: out = in[3];
-	    4: out = in[4];
-	    5: out = in[5];
-	    6: out = in[6];
-	    7: out = in[7];
-	    8: out = in[8];
-	    9: out = in[9];
-	    10: out = in[10];
-	    11: out = in[11];
-	    12: out = in[12];
-	    13: out = in[13];
-	    14: out = in[14];
-	    15: out = in[15];
-	    16: out = in[16];
-	    17: out = in[17];
-	    18: out = in[18];
-	    19: out = in[19];
-	    20: out = in[20];
-	    21: out = in[21];
-	    22: out = in[22];
-	    23: out = in[23];
-	    24: out = in[24];
-	    25: out = in[25];
-	    26: out = in[26];
-	    27: out = in[27];
-	    28: out = in[28];
-	    29: out = in[29];
-	    30: out = in[30];
-	    31: out = in[31];
-	    32: out = in[32];
-	    33: out = in[33];
-	    34: out = in[34];
-	    35: out = in[35];
-	    36: out = in[36];
-	    37: out = in[37];
-	    38: out = in[38];
-	    39: out = in[39];
-	    40: out = in[40];
-	    41: out = in[41];
-	    42: out = in[42];
-	    43: out = in[43];
-	    44: out = in[44];
-	    45: out = in[45];
-	    46: out = in[46];
-	    47: out = in[47];
-	    48: out = in[48];
-	    49: out = in[49];
-	    50: out = in[50];
-	    51: out = in[51];
-	    52: out = in[52];
-	    53: out = in[53];
-	    54: out = in[54];
-	    55: out = in[55];
-	    56: out = in[56];
-	    57: out = in[57];
-	    58: out = in[58];
-	    59: out = in[59];
-	    60: out = in[60];
-	    61: out = in[61];
-	    62: out = in[62];
-	    63: out = in[63];
-	endcase
-endmodule	
-
diff --git a/tests/hana/test_simulation_mux_8_test.v b/tests/hana/test_simulation_mux_8_test.v
deleted file mode 100644
index f53a2c57..00000000
--- a/tests/hana/test_simulation_mux_8_test.v
+++ /dev/null
@@ -1,14 +0,0 @@
-module test(input [7:0] in, input [2:0] select, output reg out);
-
-always @( in or select)
-    case (select)
-	    0: out = in[0];
-	    1: out = in[1];
-	    2: out = in[2];
-	    3: out = in[3];
-	    4: out = in[4];
-	    5: out = in[5];
-	    6: out = in[6];
-	    7: out = in[7];
-	endcase
-endmodule
diff --git a/tests/hana/test_simulation_nand.v b/tests/hana/test_simulation_nand.v
new file mode 100644
index 00000000..5e6e0f1f
--- /dev/null
+++ b/tests/hana/test_simulation_nand.v
@@ -0,0 +1,25 @@
+
+// test_simulation_nand_1_test.v
+module f1_test(input [1:0] in, output out);
+assign out = ~(in[0] & in[1]);
+endmodule
+
+// test_simulation_nand_3_test.v
+module f2_test(input [2:0] in, output out);
+assign out = !(in[0] & in[1] & in[2]);
+endmodule
+
+// test_simulation_nand_4_test.v
+module f3_test(input [2:0] in, output out);
+assign out = ~(in[0] && in[1] && in[2]);
+endmodule
+
+// test_simulation_nand_5_test.v
+module f4_test(input [3:0] in, output out);
+assign out = !(in[0] & in[1] & in[2] & in[3]);
+endmodule
+
+// test_simulation_nand_6_test.v
+module f5_test(input [3:0] in, output out);
+assign out = !(in[0] && in[1] && in[2] && in[3]);
+endmodule
diff --git a/tests/hana/test_simulation_nand_1_test.v b/tests/hana/test_simulation_nand_1_test.v
deleted file mode 100644
index d8f34ee1..00000000
--- a/tests/hana/test_simulation_nand_1_test.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module test(input [1:0] in, output out);
-assign out = ~(in[0] & in[1]);
-endmodule
diff --git a/tests/hana/test_simulation_nand_3_test.v b/tests/hana/test_simulation_nand_3_test.v
deleted file mode 100644
index 8926cebb..00000000
--- a/tests/hana/test_simulation_nand_3_test.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module test(input [2:0] in, output out);
-assign out = !(in[0] & in[1] & in[2]);
-endmodule
diff --git a/tests/hana/test_simulation_nand_4_test.v b/tests/hana/test_simulation_nand_4_test.v
deleted file mode 100644
index 703a2de4..00000000
--- a/tests/hana/test_simulation_nand_4_test.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module test(input [2:0] in, output out);
-assign out = ~(in[0] && in[1] && in[2]);
-endmodule
diff --git a/tests/hana/test_simulation_nand_5_test.v b/tests/hana/test_simulation_nand_5_test.v
deleted file mode 100644
index adef3c90..00000000
--- a/tests/hana/test_simulation_nand_5_test.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module test(input [3:0] in, output out);
-assign out = !(in[0] & in[1] & in[2] & in[3]);
-endmodule
diff --git a/tests/hana/test_simulation_nand_6_test.v b/tests/hana/test_simulation_nand_6_test.v
deleted file mode 100644
index a2136f21..00000000
--- a/tests/hana/test_simulation_nand_6_test.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module test(input [3:0] in, output out);
-assign out = !(in[0] && in[1] && in[2] && in[3]);
-endmodule
diff --git a/tests/hana/test_simulation_nor.v b/tests/hana/test_simulation_nor.v
new file mode 100644
index 00000000..d7d2bc0e
--- /dev/null
+++ b/tests/hana/test_simulation_nor.v
@@ -0,0 +1,20 @@
+
+// test_simulation_nor_1_test.v
+module f1_test(input [1:0] in, output out);
+assign out = ~(in[0] | in[1]);
+endmodule
+
+// test_simulation_nor_2_test.v
+module f2_test(input [2:0] in, output out);
+assign out = ~(in[0] | in[1] | in[2]);
+endmodule
+
+// test_simulation_nor_3_test.v
+module f3_test(input [3:0] in, output out);
+assign out = ~(in[0] | in[1] | in[2] | in[3]);
+endmodule
+
+// test_simulation_nor_4_test.v
+module f4_test(input [3:0] in, output out);
+nor mynor(out, in[0], in[1], in[2], in[3]);
+endmodule
diff --git a/tests/hana/test_simulation_nor_1_test.v b/tests/hana/test_simulation_nor_1_test.v
deleted file mode 100644
index df4e8bfa..00000000
--- a/tests/hana/test_simulation_nor_1_test.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module test(input [1:0] in, output out);
-assign out = ~(in[0] | in[1]);
-endmodule
diff --git a/tests/hana/test_simulation_nor_2_test.v b/tests/hana/test_simulation_nor_2_test.v
deleted file mode 100644
index 2cfffc45..00000000
--- a/tests/hana/test_simulation_nor_2_test.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module test(input [2:0] in, output out);
-assign out = ~(in[0] | in[1] | in[2]);
-endmodule
diff --git a/tests/hana/test_simulation_nor_3_test.v b/tests/hana/test_simulation_nor_3_test.v
deleted file mode 100644
index 9f1ef8fe..00000000
--- a/tests/hana/test_simulation_nor_3_test.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module test(input [3:0] in, output out);
-assign out = ~(in[0] | in[1] | in[2] | in[3]);
-endmodule
diff --git a/tests/hana/test_simulation_nor_4_test.v b/tests/hana/test_simulation_nor_4_test.v
deleted file mode 100644
index d8e68504..00000000
--- a/tests/hana/test_simulation_nor_4_test.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module test(input [3:0] in, output out);
-nor mynor(out, in[0], in[1], in[2], in[3]);
-endmodule
diff --git a/tests/hana/test_simulation_opt_constprop_contassign_1_test.v b/tests/hana/test_simulation_opt_constprop_contassign_1_test.v
deleted file mode 100644
index a39b58b4..00000000
--- a/tests/hana/test_simulation_opt_constprop_contassign_1_test.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module test(input in, output out);
-assign out = 1'b1;
-endmodule
diff --git a/tests/hana/test_simulation_or.v b/tests/hana/test_simulation_or.v
new file mode 100644
index 00000000..9217db80
--- /dev/null
+++ b/tests/hana/test_simulation_or.v
@@ -0,0 +1,30 @@
+
+// test_simulation_or_1_test.v
+module f1_test(input [1:0] in, output out);
+assign out = in[0] | in[1];
+endmodule
+
+// test_simulation_or_2_test.v
+module f2_test(input [1:0] in, output out);
+assign out = in[0] || in[1];
+endmodule
+
+// test_simulation_or_3_test.v
+module f3_test(input [2:0] in, output out);
+assign out = in[0] | in[1] | in[2];
+endmodule
+
+// test_simulation_or_4_test.v
+module f4_test(input [2:0] in, output out);
+assign out = in[0] || in[1] || in[2];
+endmodule
+
+// test_simulation_or_5_test.v
+module f5_test(input [3:0] in, output out);
+assign out = in[0] | in[1] | in[2] | in[3];
+endmodule
+
+// test_simulation_or_6_test.v
+module f6_test(input [3:0] in, output out);
+assign out = in[0] || in[1] || in[2] || in[3];
+endmodule
diff --git a/tests/hana/test_simulation_or_1_test.v b/tests/hana/test_simulation_or_1_test.v
deleted file mode 100644
index bdfffd3d..00000000
--- a/tests/hana/test_simulation_or_1_test.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module test(input [1:0] in, output out);
-assign out = in[0] | in[1];
-endmodule
diff --git a/tests/hana/test_simulation_or_2_test.v b/tests/hana/test_simulation_or_2_test.v
deleted file mode 100644
index 291c8c76..00000000
--- a/tests/hana/test_simulation_or_2_test.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module test(input [1:0] in, output out);
-assign out = in[0] || in[1];
-endmodule
diff --git a/tests/hana/test_simulation_or_3_test.v b/tests/hana/test_simulation_or_3_test.v
deleted file mode 100644
index ad00c708..00000000
--- a/tests/hana/test_simulation_or_3_test.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module test(input [2:0] in, output out);
-assign out = in[0] | in[1] | in[2];
-endmodule
diff --git a/tests/hana/test_simulation_or_4_test.v b/tests/hana/test_simulation_or_4_test.v
deleted file mode 100644
index 2ec57fa9..00000000
--- a/tests/hana/test_simulation_or_4_test.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module test(input [2:0] in, output out);
-assign out = in[0] || in[1] || in[2];
-endmodule
diff --git a/tests/hana/test_simulation_or_5_test.v b/tests/hana/test_simulation_or_5_test.v
deleted file mode 100644
index f6a2d14d..00000000
--- a/tests/hana/test_simulation_or_5_test.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module test(input [3:0] in, output out);
-assign out = in[0] | in[1] | in[2] | in[3];
-endmodule
diff --git a/tests/hana/test_simulation_or_6_test.v b/tests/hana/test_simulation_or_6_test.v
deleted file mode 100644
index ecd85c36..00000000
--- a/tests/hana/test_simulation_or_6_test.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module test(input [3:0] in, output out);
-assign out = in[0] || in[1] || in[2] || in[3];
-endmodule
diff --git a/tests/hana/test_simulation_seq.v b/tests/hana/test_simulation_seq.v
new file mode 100644
index 00000000..eba4e88e
--- /dev/null
+++ b/tests/hana/test_simulation_seq.v
@@ -0,0 +1,12 @@
+
+// test_simulation_seq_ff_1_test.v
+module f1_test(input in,  input clk, output reg out);
+always @(posedge clk)
+    out <= in;
+endmodule	
+
+// test_simulation_seq_ff_2_test.v
+module f2_test(input  in,  input clk,  output reg out);
+always @(negedge clk)
+   out <= in;
+endmodule	
diff --git a/tests/hana/test_simulation_seq_ff_1_test.v b/tests/hana/test_simulation_seq_ff_1_test.v
deleted file mode 100644
index 5aac49c0..00000000
--- a/tests/hana/test_simulation_seq_ff_1_test.v
+++ /dev/null
@@ -1,4 +0,0 @@
-module test(input in,  input clk, output reg out);
-always @(posedge clk)
-    out <= in;
-endmodule	
diff --git a/tests/hana/test_simulation_seq_ff_2_test.v b/tests/hana/test_simulation_seq_ff_2_test.v
deleted file mode 100644
index f1d2b7b4..00000000
--- a/tests/hana/test_simulation_seq_ff_2_test.v
+++ /dev/null
@@ -1,4 +0,0 @@
-module test(input  in,  input clk,  output reg out);
-always @(negedge clk)
-   out <= in;
-endmodule	
diff --git a/tests/hana/test_simulation_shifter.v b/tests/hana/test_simulation_shifter.v
new file mode 100644
index 00000000..8864fb0e
--- /dev/null
+++ b/tests/hana/test_simulation_shifter.v
@@ -0,0 +1,60 @@
+
+// test_simulation_shifter_left_16_test.v
+module f1_test(input [15:0] IN, input [4:0] SHIFT, output [15:0] OUT);
+
+assign OUT = IN << SHIFT;
+endmodule
+
+// test_simulation_shifter_left_32_test.v
+module f2_test(input [31:0] IN, input [5:0] SHIFT, output [31:0] OUT);
+
+assign OUT = IN << SHIFT;
+endmodule
+
+// test_simulation_shifter_left_4_test.v
+module f3_test(input [3:0] IN, input [2:0] SHIFT, output [3:0] OUT);
+
+assign OUT = IN << SHIFT;
+endmodule
+
+// test_simulation_shifter_left_64_test.v
+module f4_test(input [63:0] IN, input [6:0] SHIFT, output [63:0] OUT);
+
+assign OUT = IN << SHIFT;
+endmodule
+
+// test_simulation_shifter_left_8_test.v
+module f5_test(input [7:0] IN, input [3:0] SHIFT, output [7:0] OUT);
+
+assign OUT = IN << SHIFT;
+endmodule
+
+// test_simulation_shifter_right_16_test.v
+module f6_test(input [15:0] IN, input [4:0] SHIFT, output [15:0] OUT);
+
+assign OUT = IN >> SHIFT;
+endmodule
+
+// test_simulation_shifter_right_32_test.v
+module f7_test(input [31:0] IN, input [5:0] SHIFT, output [31:0] OUT);
+
+assign OUT = IN >> SHIFT;
+endmodule
+
+// test_simulation_shifter_right_4_test.v
+module f8_test(input [3:0] IN, input [2:0] SHIFT, output [3:0] OUT);
+
+assign OUT = IN >> SHIFT;
+endmodule
+
+// test_simulation_shifter_right_64_test.v
+module f9_test(input [63:0] IN, input [6:0] SHIFT, output [63:0] OUT);
+
+assign OUT = IN >> SHIFT;
+endmodule
+
+// test_simulation_shifter_right_8_test.v
+module f10_test(input [7:0] IN, input [3:0] SHIFT, output [7:0] OUT);
+
+assign OUT = IN >> SHIFT;
+endmodule
diff --git a/tests/hana/test_simulation_shifter_left_16_test.v b/tests/hana/test_simulation_shifter_left_16_test.v
deleted file mode 100644
index a57dac49..00000000
--- a/tests/hana/test_simulation_shifter_left_16_test.v
+++ /dev/null
@@ -1,4 +0,0 @@
-module test(input [15:0] IN, input [4:0] SHIFT, output [15:0] OUT);
-
-assign OUT = IN << SHIFT;
-endmodule
diff --git a/tests/hana/test_simulation_shifter_left_32_test.v b/tests/hana/test_simulation_shifter_left_32_test.v
deleted file mode 100644
index 672938ac..00000000
--- a/tests/hana/test_simulation_shifter_left_32_test.v
+++ /dev/null
@@ -1,4 +0,0 @@
-module test(input [31:0] IN, input [5:0] SHIFT, output [31:0] OUT);
-
-assign OUT = IN << SHIFT;
-endmodule
diff --git a/tests/hana/test_simulation_shifter_left_4_test.v b/tests/hana/test_simulation_shifter_left_4_test.v
deleted file mode 100644
index c525401f..00000000
--- a/tests/hana/test_simulation_shifter_left_4_test.v
+++ /dev/null
@@ -1,4 +0,0 @@
-module test(input [3:0] IN, input [2:0] SHIFT, output [3:0] OUT);
-
-assign OUT = IN << SHIFT;
-endmodule
diff --git a/tests/hana/test_simulation_shifter_left_64_test.v b/tests/hana/test_simulation_shifter_left_64_test.v
deleted file mode 100644
index 276a7c5a..00000000
--- a/tests/hana/test_simulation_shifter_left_64_test.v
+++ /dev/null
@@ -1,4 +0,0 @@
-module test(input [63:0] IN, input [6:0] SHIFT, output [63:0] OUT);
-
-assign OUT = IN << SHIFT;
-endmodule
diff --git a/tests/hana/test_simulation_shifter_left_8_test.v b/tests/hana/test_simulation_shifter_left_8_test.v
deleted file mode 100644
index c1727700..00000000
--- a/tests/hana/test_simulation_shifter_left_8_test.v
+++ /dev/null
@@ -1,4 +0,0 @@
-module test(input [7:0] IN, input [3:0] SHIFT, output [7:0] OUT);
-
-assign OUT = IN << SHIFT;
-endmodule
diff --git a/tests/hana/test_simulation_shifter_right_16_test.v b/tests/hana/test_simulation_shifter_right_16_test.v
deleted file mode 100644
index 6152adc0..00000000
--- a/tests/hana/test_simulation_shifter_right_16_test.v
+++ /dev/null
@@ -1,4 +0,0 @@
-module test(input [15:0] IN, input [4:0] SHIFT, output [15:0] OUT);
-
-assign OUT = IN >> SHIFT;
-endmodule
diff --git a/tests/hana/test_simulation_shifter_right_32_test.v b/tests/hana/test_simulation_shifter_right_32_test.v
deleted file mode 100644
index e910cdd6..00000000
--- a/tests/hana/test_simulation_shifter_right_32_test.v
+++ /dev/null
@@ -1,4 +0,0 @@
-module test(input [31:0] IN, input [5:0] SHIFT, output [31:0] OUT);
-
-assign OUT = IN >> SHIFT;
-endmodule
diff --git a/tests/hana/test_simulation_shifter_right_4_test.v b/tests/hana/test_simulation_shifter_right_4_test.v
deleted file mode 100644
index 608c196d..00000000
--- a/tests/hana/test_simulation_shifter_right_4_test.v
+++ /dev/null
@@ -1,4 +0,0 @@
-module test(input [3:0] IN, input [2:0] SHIFT, output [3:0] OUT);
-
-assign OUT = IN >> SHIFT;
-endmodule
diff --git a/tests/hana/test_simulation_shifter_right_64_test.v b/tests/hana/test_simulation_shifter_right_64_test.v
deleted file mode 100644
index c26d5938..00000000
--- a/tests/hana/test_simulation_shifter_right_64_test.v
+++ /dev/null
@@ -1,4 +0,0 @@
-module test(input [63:0] IN, input [6:0] SHIFT, output [63:0] OUT);
-
-assign OUT = IN >> SHIFT;
-endmodule
diff --git a/tests/hana/test_simulation_shifter_right_8_test.v b/tests/hana/test_simulation_shifter_right_8_test.v
deleted file mode 100644
index a91c594e..00000000
--- a/tests/hana/test_simulation_shifter_right_8_test.v
+++ /dev/null
@@ -1,4 +0,0 @@
-module test(input [7:0] IN, input [3:0] SHIFT, output [7:0] OUT);
-
-assign OUT = IN >> SHIFT;
-endmodule
diff --git a/tests/hana/test_simulation_sop.v b/tests/hana/test_simulation_sop.v
new file mode 100644
index 00000000..79870cf0
--- /dev/null
+++ b/tests/hana/test_simulation_sop.v
@@ -0,0 +1,65 @@
+
+// test_simulation_sop_basic_10_test.v
+module f1_test(input [1:0] in, input select, output reg out);
+
+always @( in or select)
+    case (select)
+	    0: out = in[0];
+	    1: out = in[1];
+	endcase
+endmodule	
+
+// test_simulation_sop_basic_11_test.v
+module f2_test(input [3:0] in, input [1:0] select, output reg out);
+
+always @( in or select)
+    case (select)
+	    0: out = in[0];
+	    1: out = in[1];
+	    2: out = in[2];
+	    3: out = in[3];
+	endcase
+endmodule	
+
+// test_simulation_sop_basic_12_test.v
+module f3_test(input [7:0] in, input [2:0] select, output reg out);
+
+always @( in or select)
+    case (select)
+	    0: out = in[0];
+	    1: out = in[1];
+	    2: out = in[2];
+	    3: out = in[3];
+	    4: out = in[4];
+	    5: out = in[5];
+	    6: out = in[6];
+	    7: out = in[7];
+	endcase
+endmodule
+
+// test_simulation_sop_basic_18_test.v
+module f4_test(input [7:0] in, output out);
+
+assign out = ~^in;
+
+endmodule
+
+// test_simulation_sop_basic_3_test.v
+module f5_test(input in, output out);
+assign out = ~in;
+endmodule
+
+// test_simulation_sop_basic_7_test.v
+module f6_test(input in, output out);
+assign out = in;
+endmodule
+
+// test_simulation_sop_basic_8_test.v
+module f7_test(output out);
+assign out = 1'b0;
+endmodule
+
+// test_simulation_sop_basic_9_test.v
+module f8_test(input in, output out);
+assign out = ~in;
+endmodule
diff --git a/tests/hana/test_simulation_sop_basic_10_test.v b/tests/hana/test_simulation_sop_basic_10_test.v
deleted file mode 100644
index bc676c70..00000000
--- a/tests/hana/test_simulation_sop_basic_10_test.v
+++ /dev/null
@@ -1,8 +0,0 @@
-module test(input [1:0] in, input select, output reg out);
-
-always @( in or select)
-    case (select)
-	    0: out = in[0];
-	    1: out = in[1];
-	endcase
-endmodule	
diff --git a/tests/hana/test_simulation_sop_basic_11_test.v b/tests/hana/test_simulation_sop_basic_11_test.v
deleted file mode 100644
index 6a112c6a..00000000
--- a/tests/hana/test_simulation_sop_basic_11_test.v
+++ /dev/null
@@ -1,10 +0,0 @@
-module test(input [3:0] in, input [1:0] select, output reg out);
-
-always @( in or select)
-    case (select)
-	    0: out = in[0];
-	    1: out = in[1];
-	    2: out = in[2];
-	    3: out = in[3];
-	endcase
-endmodule	
diff --git a/tests/hana/test_simulation_sop_basic_12_test.v b/tests/hana/test_simulation_sop_basic_12_test.v
deleted file mode 100644
index f53a2c57..00000000
--- a/tests/hana/test_simulation_sop_basic_12_test.v
+++ /dev/null
@@ -1,14 +0,0 @@
-module test(input [7:0] in, input [2:0] select, output reg out);
-
-always @( in or select)
-    case (select)
-	    0: out = in[0];
-	    1: out = in[1];
-	    2: out = in[2];
-	    3: out = in[3];
-	    4: out = in[4];
-	    5: out = in[5];
-	    6: out = in[6];
-	    7: out = in[7];
-	endcase
-endmodule
diff --git a/tests/hana/test_simulation_sop_basic_18_test.v b/tests/hana/test_simulation_sop_basic_18_test.v
deleted file mode 100644
index 03fc35b3..00000000
--- a/tests/hana/test_simulation_sop_basic_18_test.v
+++ /dev/null
@@ -1,5 +0,0 @@
-module test(input [7:0] in, output out);
-
-assign out = ~^in;
-
-endmodule
diff --git a/tests/hana/test_simulation_sop_basic_3_test.v b/tests/hana/test_simulation_sop_basic_3_test.v
deleted file mode 100644
index 81759c25..00000000
--- a/tests/hana/test_simulation_sop_basic_3_test.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module test(input in, output out);
-assign out = ~in;
-endmodule
diff --git a/tests/hana/test_simulation_sop_basic_7_test.v b/tests/hana/test_simulation_sop_basic_7_test.v
deleted file mode 100644
index e9bb7f61..00000000
--- a/tests/hana/test_simulation_sop_basic_7_test.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module test(input in, output out);
-assign out = in;
-endmodule
diff --git a/tests/hana/test_simulation_sop_basic_8_test.v b/tests/hana/test_simulation_sop_basic_8_test.v
deleted file mode 100644
index a51ead0b..00000000
--- a/tests/hana/test_simulation_sop_basic_8_test.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module test(output out);
-assign out = 1'b0;
-endmodule
diff --git a/tests/hana/test_simulation_sop_basic_9_test.v b/tests/hana/test_simulation_sop_basic_9_test.v
deleted file mode 100644
index 81759c25..00000000
--- a/tests/hana/test_simulation_sop_basic_9_test.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module test(input in, output out);
-assign out = ~in;
-endmodule
diff --git a/tests/hana/test_simulation_techmap.v b/tests/hana/test_simulation_techmap.v
new file mode 100644
index 00000000..88e24d0e
--- /dev/null
+++ b/tests/hana/test_simulation_techmap.v
@@ -0,0 +1,172 @@
+
+// test_simulation_techmap_buf_test.v
+module f1_test(input in, output out);
+assign out = in;
+endmodule
+
+// test_simulation_techmap_inv_test.v
+module f2_test(input in, output out);
+assign out = ~in;
+endmodule
+
+// test_simulation_techmap_mux_0_test.v
+module f3_test(input [1:0] in, input select, output reg out);
+
+always @( in or select)
+    case (select)
+	    0: out = in[0];
+	    1: out = in[1];
+	endcase
+endmodule	
+
+// test_simulation_techmap_mux_128_test.v
+module f4_test(input [127:0] in, input [6:0] select, output reg out);
+
+always @( in or select)
+    case (select)
+	    0: out = in[0];
+	    1: out = in[1];
+	    2: out = in[2];
+	    3: out = in[3];
+	    4: out = in[4];
+	    5: out = in[5];
+	    6: out = in[6];
+	    7: out = in[7];
+	    8: out = in[8];
+	    9: out = in[9];
+	    10: out = in[10];
+	    11: out = in[11];
+	    12: out = in[12];
+	    13: out = in[13];
+	    14: out = in[14];
+	    15: out = in[15];
+	    16: out = in[16];
+	    17: out = in[17];
+	    18: out = in[18];
+	    19: out = in[19];
+	    20: out = in[20];
+	    21: out = in[21];
+	    22: out = in[22];
+	    23: out = in[23];
+	    24: out = in[24];
+	    25: out = in[25];
+	    26: out = in[26];
+	    27: out = in[27];
+	    28: out = in[28];
+	    29: out = in[29];
+	    30: out = in[30];
+	    31: out = in[31];
+	    32: out = in[32];
+	    33: out = in[33];
+	    34: out = in[34];
+	    35: out = in[35];
+	    36: out = in[36];
+	    37: out = in[37];
+	    38: out = in[38];
+	    39: out = in[39];
+	    40: out = in[40];
+	    41: out = in[41];
+	    42: out = in[42];
+	    43: out = in[43];
+	    44: out = in[44];
+	    45: out = in[45];
+	    46: out = in[46];
+	    47: out = in[47];
+	    48: out = in[48];
+	    49: out = in[49];
+	    50: out = in[50];
+	    51: out = in[51];
+	    52: out = in[52];
+	    53: out = in[53];
+	    54: out = in[54];
+	    55: out = in[55];
+	    56: out = in[56];
+	    57: out = in[57];
+	    58: out = in[58];
+	    59: out = in[59];
+	    60: out = in[60];
+	    61: out = in[61];
+	    62: out = in[62];
+	    63: out = in[63];
+	    64: out = in[64];
+	    65: out = in[65];
+	    66: out = in[66];
+	    67: out = in[67];
+	    68: out = in[68];
+	    69: out = in[69];
+	    70: out = in[70];
+	    71: out = in[71];
+	    72: out = in[72];
+	    73: out = in[73];
+	    74: out = in[74];
+	    75: out = in[75];
+	    76: out = in[76];
+	    77: out = in[77];
+	    78: out = in[78];
+	    79: out = in[79];
+	    80: out = in[80];
+	    81: out = in[81];
+	    82: out = in[82];
+	    83: out = in[83];
+	    84: out = in[84];
+	    85: out = in[85];
+	    86: out = in[86];
+	    87: out = in[87];
+	    88: out = in[88];
+	    89: out = in[89];
+	    90: out = in[90];
+	    91: out = in[91];
+	    92: out = in[92];
+	    93: out = in[93];
+	    94: out = in[94];
+	    95: out = in[95];
+	    96: out = in[96];
+	    97: out = in[97];
+	    98: out = in[98];
+	    99: out = in[99];
+	    100: out = in[100];
+	    101: out = in[101];
+	    102: out = in[102];
+	    103: out = in[103];
+	    104: out = in[104];
+	    105: out = in[105];
+	    106: out = in[106];
+	    107: out = in[107];
+	    108: out = in[108];
+	    109: out = in[109];
+	    110: out = in[110];
+	    111: out = in[111];
+	    112: out = in[112];
+	    113: out = in[113];
+	    114: out = in[114];
+	    115: out = in[115];
+	    116: out = in[116];
+	    117: out = in[117];
+	    118: out = in[118];
+	    119: out = in[119];
+	    120: out = in[120];
+	    121: out = in[121];
+	    122: out = in[122];
+	    123: out = in[123];
+	    124: out = in[124];
+	    125: out = in[125];
+	    126: out = in[126];
+	    127: out = in[127];
+	endcase
+endmodule
+
+// test_simulation_techmap_mux_8_test.v
+module f5_test(input [7:0] in, input [2:0] select, output reg out);
+
+always @( in or select)
+    case (select)
+	    0: out = in[0];
+	    1: out = in[1];
+	    2: out = in[2];
+	    3: out = in[3];
+	    4: out = in[4];
+	    5: out = in[5];
+	    6: out = in[6];
+	    7: out = in[7];
+	endcase
+endmodule
diff --git a/tests/hana/test_simulation_techmap_and_19_tech.v b/tests/hana/test_simulation_techmap_and_19_tech.v
deleted file mode 100644
index 2491087c..00000000
--- a/tests/hana/test_simulation_techmap_and_19_tech.v
+++ /dev/null
@@ -1,7 +0,0 @@
-module TECH_AND18(input [17:0] in, output out);
-assign out = &in;
-endmodule
-
-module TECH_AND4(input [3:0] in, output out);
-assign out = &in;
-endmodule
diff --git a/tests/hana/test_simulation_techmap_and_5_tech.v b/tests/hana/test_simulation_techmap_and_5_tech.v
deleted file mode 100644
index 6ec6a61c..00000000
--- a/tests/hana/test_simulation_techmap_and_5_tech.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module TECH_AND5(input [4:0] in, output out);
-assign out = &in;
-endmodule
diff --git a/tests/hana/test_simulation_techmap_buf_test.v b/tests/hana/test_simulation_techmap_buf_test.v
deleted file mode 100644
index e9bb7f61..00000000
--- a/tests/hana/test_simulation_techmap_buf_test.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module test(input in, output out);
-assign out = in;
-endmodule
diff --git a/tests/hana/test_simulation_techmap_inv_test.v b/tests/hana/test_simulation_techmap_inv_test.v
deleted file mode 100644
index 81759c25..00000000
--- a/tests/hana/test_simulation_techmap_inv_test.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module test(input in, output out);
-assign out = ~in;
-endmodule
diff --git a/tests/hana/test_simulation_techmap_mux_0_test.v b/tests/hana/test_simulation_techmap_mux_0_test.v
deleted file mode 100644
index bc676c70..00000000
--- a/tests/hana/test_simulation_techmap_mux_0_test.v
+++ /dev/null
@@ -1,8 +0,0 @@
-module test(input [1:0] in, input select, output reg out);
-
-always @( in or select)
-    case (select)
-	    0: out = in[0];
-	    1: out = in[1];
-	endcase
-endmodule	
diff --git a/tests/hana/test_simulation_techmap_mux_128_test.v b/tests/hana/test_simulation_techmap_mux_128_test.v
deleted file mode 100644
index 544c016a..00000000
--- a/tests/hana/test_simulation_techmap_mux_128_test.v
+++ /dev/null
@@ -1,134 +0,0 @@
-module test(input [127:0] in, input [6:0] select, output reg out);
-
-always @( in or select)
-    case (select)
-	    0: out = in[0];
-	    1: out = in[1];
-	    2: out = in[2];
-	    3: out = in[3];
-	    4: out = in[4];
-	    5: out = in[5];
-	    6: out = in[6];
-	    7: out = in[7];
-	    8: out = in[8];
-	    9: out = in[9];
-	    10: out = in[10];
-	    11: out = in[11];
-	    12: out = in[12];
-	    13: out = in[13];
-	    14: out = in[14];
-	    15: out = in[15];
-	    16: out = in[16];
-	    17: out = in[17];
-	    18: out = in[18];
-	    19: out = in[19];
-	    20: out = in[20];
-	    21: out = in[21];
-	    22: out = in[22];
-	    23: out = in[23];
-	    24: out = in[24];
-	    25: out = in[25];
-	    26: out = in[26];
-	    27: out = in[27];
-	    28: out = in[28];
-	    29: out = in[29];
-	    30: out = in[30];
-	    31: out = in[31];
-	    32: out = in[32];
-	    33: out = in[33];
-	    34: out = in[34];
-	    35: out = in[35];
-	    36: out = in[36];
-	    37: out = in[37];
-	    38: out = in[38];
-	    39: out = in[39];
-	    40: out = in[40];
-	    41: out = in[41];
-	    42: out = in[42];
-	    43: out = in[43];
-	    44: out = in[44];
-	    45: out = in[45];
-	    46: out = in[46];
-	    47: out = in[47];
-	    48: out = in[48];
-	    49: out = in[49];
-	    50: out = in[50];
-	    51: out = in[51];
-	    52: out = in[52];
-	    53: out = in[53];
-	    54: out = in[54];
-	    55: out = in[55];
-	    56: out = in[56];
-	    57: out = in[57];
-	    58: out = in[58];
-	    59: out = in[59];
-	    60: out = in[60];
-	    61: out = in[61];
-	    62: out = in[62];
-	    63: out = in[63];
-	    64: out = in[64];
-	    65: out = in[65];
-	    66: out = in[66];
-	    67: out = in[67];
-	    68: out = in[68];
-	    69: out = in[69];
-	    70: out = in[70];
-	    71: out = in[71];
-	    72: out = in[72];
-	    73: out = in[73];
-	    74: out = in[74];
-	    75: out = in[75];
-	    76: out = in[76];
-	    77: out = in[77];
-	    78: out = in[78];
-	    79: out = in[79];
-	    80: out = in[80];
-	    81: out = in[81];
-	    82: out = in[82];
-	    83: out = in[83];
-	    84: out = in[84];
-	    85: out = in[85];
-	    86: out = in[86];
-	    87: out = in[87];
-	    88: out = in[88];
-	    89: out = in[89];
-	    90: out = in[90];
-	    91: out = in[91];
-	    92: out = in[92];
-	    93: out = in[93];
-	    94: out = in[94];
-	    95: out = in[95];
-	    96: out = in[96];
-	    97: out = in[97];
-	    98: out = in[98];
-	    99: out = in[99];
-	    100: out = in[100];
-	    101: out = in[101];
-	    102: out = in[102];
-	    103: out = in[103];
-	    104: out = in[104];
-	    105: out = in[105];
-	    106: out = in[106];
-	    107: out = in[107];
-	    108: out = in[108];
-	    109: out = in[109];
-	    110: out = in[110];
-	    111: out = in[111];
-	    112: out = in[112];
-	    113: out = in[113];
-	    114: out = in[114];
-	    115: out = in[115];
-	    116: out = in[116];
-	    117: out = in[117];
-	    118: out = in[118];
-	    119: out = in[119];
-	    120: out = in[120];
-	    121: out = in[121];
-	    122: out = in[122];
-	    123: out = in[123];
-	    124: out = in[124];
-	    125: out = in[125];
-	    126: out = in[126];
-	    127: out = in[127];
-	endcase
-endmodule
diff --git a/tests/hana/test_simulation_techmap_mux_8_test.v b/tests/hana/test_simulation_techmap_mux_8_test.v
deleted file mode 100644
index f53a2c57..00000000
--- a/tests/hana/test_simulation_techmap_mux_8_test.v
+++ /dev/null
@@ -1,14 +0,0 @@
-module test(input [7:0] in, input [2:0] select, output reg out);
-
-always @( in or select)
-    case (select)
-	    0: out = in[0];
-	    1: out = in[1];
-	    2: out = in[2];
-	    3: out = in[3];
-	    4: out = in[4];
-	    5: out = in[5];
-	    6: out = in[6];
-	    7: out = in[7];
-	endcase
-endmodule
diff --git a/tests/hana/test_simulation_techmap_nand_19_tech.v b/tests/hana/test_simulation_techmap_nand_19_tech.v
deleted file mode 100644
index 6a119e1e..00000000
--- a/tests/hana/test_simulation_techmap_nand_19_tech.v
+++ /dev/null
@@ -1,11 +0,0 @@
-module TECH_NAND18(input [17:0] in, output out);
-assign out = ~(&in);
-endmodule
-
-module TECH_NAND4(input [3:0] in, output out);
-assign out = ~(&in);
-endmodule
-
-module TECH_NAND2(input [1:0] in, output out);
-assign out = ~(&in);
-endmodule
diff --git a/tests/hana/test_simulation_techmap_nand_2_tech.v b/tests/hana/test_simulation_techmap_nand_2_tech.v
deleted file mode 100644
index 6a119e1e..00000000
--- a/tests/hana/test_simulation_techmap_nand_2_tech.v
+++ /dev/null
@@ -1,11 +0,0 @@
-module TECH_NAND18(input [17:0] in, output out);
-assign out = ~(&in);
-endmodule
-
-module TECH_NAND4(input [3:0] in, output out);
-assign out = ~(&in);
-endmodule
-
-module TECH_NAND2(input [1:0] in, output out);
-assign out = ~(&in);
-endmodule
diff --git a/tests/hana/test_simulation_techmap_nand_5_tech.v b/tests/hana/test_simulation_techmap_nand_5_tech.v
deleted file mode 100644
index 6a119e1e..00000000
--- a/tests/hana/test_simulation_techmap_nand_5_tech.v
+++ /dev/null
@@ -1,11 +0,0 @@
-module TECH_NAND18(input [17:0] in, output out);
-assign out = ~(&in);
-endmodule
-
-module TECH_NAND4(input [3:0] in, output out);
-assign out = ~(&in);
-endmodule
-
-module TECH_NAND2(input [1:0] in, output out);
-assign out = ~(&in);
-endmodule
diff --git a/tests/hana/test_simulation_techmap_nor_19_tech.v b/tests/hana/test_simulation_techmap_nor_19_tech.v
deleted file mode 100644
index 89fb2c7e..00000000
--- a/tests/hana/test_simulation_techmap_nor_19_tech.v
+++ /dev/null
@@ -1,11 +0,0 @@
-module TECH_NOR18(input [17:0] in, output out);
-assign out = ~(|in);
-endmodule
-
-module TECH_NOR4(input [3:0] in, output out);
-assign out = ~(|in);
-endmodule
-
-module TECH_NOR2(input [1:0] in, output out);
-assign out = ~(|in);
-endmodule
diff --git a/tests/hana/test_simulation_techmap_nor_2_tech.v b/tests/hana/test_simulation_techmap_nor_2_tech.v
deleted file mode 100644
index 89fb2c7e..00000000
--- a/tests/hana/test_simulation_techmap_nor_2_tech.v
+++ /dev/null
@@ -1,11 +0,0 @@
-module TECH_NOR18(input [17:0] in, output out);
-assign out = ~(|in);
-endmodule
-
-module TECH_NOR4(input [3:0] in, output out);
-assign out = ~(|in);
-endmodule
-
-module TECH_NOR2(input [1:0] in, output out);
-assign out = ~(|in);
-endmodule
diff --git a/tests/hana/test_simulation_techmap_nor_5_tech.v b/tests/hana/test_simulation_techmap_nor_5_tech.v
deleted file mode 100644
index 89fb2c7e..00000000
--- a/tests/hana/test_simulation_techmap_nor_5_tech.v
+++ /dev/null
@@ -1,11 +0,0 @@
-module TECH_NOR18(input [17:0] in, output out);
-assign out = ~(|in);
-endmodule
-
-module TECH_NOR4(input [3:0] in, output out);
-assign out = ~(|in);
-endmodule
-
-module TECH_NOR2(input [1:0] in, output out);
-assign out = ~(|in);
-endmodule
diff --git a/tests/hana/test_simulation_techmap_or_19_tech.v b/tests/hana/test_simulation_techmap_or_19_tech.v
deleted file mode 100644
index 745d7b71..00000000
--- a/tests/hana/test_simulation_techmap_or_19_tech.v
+++ /dev/null
@@ -1,7 +0,0 @@
-module TECH_OR18(input [17:0] in, output out);
-assign out = |in;
-endmodule
-
-module TECH_OR4(input [3:0] in, output out);
-assign out = |in;
-endmodule
diff --git a/tests/hana/test_simulation_techmap_or_5_tech.v b/tests/hana/test_simulation_techmap_or_5_tech.v
deleted file mode 100644
index 05c38b67..00000000
--- a/tests/hana/test_simulation_techmap_or_5_tech.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module TECH_OR5(input [4:0] in, output out);
-assign out = |in;
-endmodule
diff --git a/tests/hana/test_simulation_techmap_tech.v b/tests/hana/test_simulation_techmap_tech.v
new file mode 100644
index 00000000..60aeca5c
--- /dev/null
+++ b/tests/hana/test_simulation_techmap_tech.v
@@ -0,0 +1,143 @@
+
+// test_simulation_techmap_and_19_tech.v
+module f1_TECH_AND18(input [17:0] in, output out);
+assign out = &in;
+endmodule
+
+module f1_TECH_AND4(input [3:0] in, output out);
+assign out = &in;
+endmodule
+
+// test_simulation_techmap_and_5_tech.v
+module f2_TECH_AND5(input [4:0] in, output out);
+assign out = &in;
+endmodule
+
+// test_simulation_techmap_nand_19_tech.v
+module f3_TECH_NAND18(input [17:0] in, output out);
+assign out = ~(&in);
+endmodule
+
+module f3_TECH_NAND4(input [3:0] in, output out);
+assign out = ~(&in);
+endmodule
+
+module f3_TECH_NAND2(input [1:0] in, output out);
+assign out = ~(&in);
+endmodule
+
+// test_simulation_techmap_nand_2_tech.v
+module f4_TECH_NAND18(input [17:0] in, output out);
+assign out = ~(&in);
+endmodule
+
+module f4_TECH_NAND4(input [3:0] in, output out);
+assign out = ~(&in);
+endmodule
+
+module f4_TECH_NAND2(input [1:0] in, output out);
+assign out = ~(&in);
+endmodule
+
+// test_simulation_techmap_nand_5_tech.v
+module f5_TECH_NAND18(input [17:0] in, output out);
+assign out = ~(&in);
+endmodule
+
+module f5_TECH_NAND4(input [3:0] in, output out);
+assign out = ~(&in);
+endmodule
+
+module f5_TECH_NAND2(input [1:0] in, output out);
+assign out = ~(&in);
+endmodule
+
+// test_simulation_techmap_nor_19_tech.v
+module f6_TECH_NOR18(input [17:0] in, output out);
+assign out = ~(|in);
+endmodule
+
+module f6_TECH_NOR4(input [3:0] in, output out);
+assign out = ~(|in);
+endmodule
+
+module f6_TECH_NOR2(input [1:0] in, output out);
+assign out = ~(|in);
+endmodule
+
+// test_simulation_techmap_nor_2_tech.v
+module f7_TECH_NOR18(input [17:0] in, output out);
+assign out = ~(|in);
+endmodule
+
+module f7_TECH_NOR4(input [3:0] in, output out);
+assign out = ~(|in);
+endmodule
+
+module f7_TECH_NOR2(input [1:0] in, output out);
+assign out = ~(|in);
+endmodule
+
+// test_simulation_techmap_nor_5_tech.v
+module f8_TECH_NOR18(input [17:0] in, output out);
+assign out = ~(|in);
+endmodule
+
+module f8_TECH_NOR4(input [3:0] in, output out);
+assign out = ~(|in);
+endmodule
+
+module f8_TECH_NOR2(input [1:0] in, output out);
+assign out = ~(|in);
+endmodule
+
+// test_simulation_techmap_or_19_tech.v
+module f9_TECH_OR18(input [17:0] in, output out);
+assign out = |in;
+endmodule
+
+module f9_TECH_OR4(input [3:0] in, output out);
+assign out = |in;
+endmodule
+
+// test_simulation_techmap_or_5_tech.v
+module f10_TECH_OR5(input [4:0] in, output out);
+assign out = |in;
+endmodule
+
+// test_simulation_techmap_xnor_2_tech.v
+module f11_TECH_XOR5(input [4:0] in, output out);
+assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4];
+endmodule
+module f11_TECH_XOR2(input [1:0] in, output out);
+assign out = in[0] ^ in[1];
+endmodule
+
+// test_simulation_techmap_xnor_5_tech.v
+module f12_TECH_XOR5(input [4:0] in, output out);
+assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4];
+endmodule
+module f12_TECH_XOR2(input [1:0] in, output out);
+assign out = in[0] ^ in[1];
+endmodule
+
+// test_simulation_techmap_xor_19_tech.v
+module f13_TECH_XOR2(input [1:0] in, output out);
+assign out = in[0] ^ in[1];
+endmodule
+
+// test_simulation_techmap_xor_2_tech.v
+module f14_TECH_XOR5(input [4:0] in, output out);
+assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4];
+endmodule
+module f14_TECH_XOR2(input [1:0] in, output out);
+assign out = in[0] ^ in[1];
+endmodule
+
+// test_simulation_techmap_xor_5_tech.v
+module f15_TECH_XOR5(input [4:0] in, output out);
+assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4];
+endmodule
+module f15_TECH_XOR2(input [1:0] in, output out);
+assign out = in[0] ^ in[1];
+endmodule
diff --git a/tests/hana/test_simulation_techmap_xnor_2_tech.v b/tests/hana/test_simulation_techmap_xnor_2_tech.v
deleted file mode 100644
index 4eb05683..00000000
--- a/tests/hana/test_simulation_techmap_xnor_2_tech.v
+++ /dev/null
@@ -1,6 +0,0 @@
-module TECH_XOR5(input [4:0] in, output out);
-assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4];
-endmodule
-module TECH_XOR2(input [1:0] in, output out);
-assign out = in[0] ^ in[1];
-endmodule
diff --git a/tests/hana/test_simulation_techmap_xnor_5_tech.v b/tests/hana/test_simulation_techmap_xnor_5_tech.v
deleted file mode 100644
index 4eb05683..00000000
--- a/tests/hana/test_simulation_techmap_xnor_5_tech.v
+++ /dev/null
@@ -1,6 +0,0 @@
-module TECH_XOR5(input [4:0] in, output out);
-assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4];
-endmodule
-module TECH_XOR2(input [1:0] in, output out);
-assign out = in[0] ^ in[1];
-endmodule
diff --git a/tests/hana/test_simulation_techmap_xor_19_tech.v b/tests/hana/test_simulation_techmap_xor_19_tech.v
deleted file mode 100644
index 2042a0ad..00000000
--- a/tests/hana/test_simulation_techmap_xor_19_tech.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module TECH_XOR2(input [1:0] in, output out);
-assign out = in[0] ^ in[1];
-endmodule
diff --git a/tests/hana/test_simulation_techmap_xor_2_tech.v b/tests/hana/test_simulation_techmap_xor_2_tech.v
deleted file mode 100644
index 4eb05683..00000000
--- a/tests/hana/test_simulation_techmap_xor_2_tech.v
+++ /dev/null
@@ -1,6 +0,0 @@
-module TECH_XOR5(input [4:0] in, output out);
-assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4];
-endmodule
-module TECH_XOR2(input [1:0] in, output out);
-assign out = in[0] ^ in[1];
-endmodule
diff --git a/tests/hana/test_simulation_techmap_xor_5_tech.v b/tests/hana/test_simulation_techmap_xor_5_tech.v
deleted file mode 100644
index 4eb05683..00000000
--- a/tests/hana/test_simulation_techmap_xor_5_tech.v
+++ /dev/null
@@ -1,6 +0,0 @@
-module TECH_XOR5(input [4:0] in, output out);
-assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4];
-endmodule
-module TECH_XOR2(input [1:0] in, output out);
-assign out = in[0] ^ in[1];
-endmodule
diff --git a/tests/hana/test_simulation_tribuf_2_test.v b/tests/hana/test_simulation_tribuf_2_test.v
deleted file mode 100644
index 1e82aaf0..00000000
--- a/tests/hana/test_simulation_tribuf_2_test.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module test(input [1:0] in, input enable, output [1:0] out);
-assign out = enable ? in : 2'bzz;
-endmodule
diff --git a/tests/hana/test_simulation_vlib.v b/tests/hana/test_simulation_vlib.v
new file mode 100644
index 00000000..7d3af09c
--- /dev/null
+++ b/tests/hana/test_simulation_vlib.v
@@ -0,0 +1,65 @@
+// test_simulation_mod_1_xx.v
+module f1_test(in1, in2, out);
+input in1;
+input in2;
+output out;
+
+wire  synth_net_0;
+wire  synth_net_1;
+BUF synth_BUF_0(.in(synth_net_1), .out(out
+    ));
+DIV1 synth_DIV(.in1(in1), .in2(in2), .rem(synth_net_0), .out(synth_net_1
+    ));
+endmodule
+
+// test_simulation_always_31_tt.v
+module f2_test(clk, cond, data);
+input cond;
+input clk;
+output data;
+
+wire  synth_net;
+wire  synth_net_0;
+wire  synth_net_1;
+wire  synth_net_2;
+
+wire  synth_net_3;
+wire  synth_net_4;
+wire  synth_net_5;
+wire  synth_net_6;
+
+wire  synth_net_7;
+wire  synth_net_8;
+wire  synth_net_9;
+wire  synth_net_10;
+
+wire  synth_net_11;
+wire  tmp;
+AND2 synth_AND(.in({synth_net_0, synth_net_1}), .
+    out(synth_net_2));
+AND2 synth_AND_0(.in({synth_net_3, synth_net_4}), .out(
+    synth_net_5));
+AND2 synth_AND_1(.in({synth_net_6, synth_net_7}), .out(
+    synth_net_8));
+AND2 synth_AND_2(.in({synth_net_9, synth_net_10}), .out(
+    synth_net_11));
+BUF synth_BUF(.in(synth_net), .out(synth_net_0));
+BUF 
+    synth_BUF_0(.in(data), .out(synth_net_3));
+BUF synth_BUF_1(.in(synth_net_8)
+    , .out(tmp));
+BUF synth_BUF_2(.in(tmp), .out(synth_net_9));
+MUX2 synth_MUX(.
+    in({synth_net_2, synth_net_5}), .select(cond), .out(synth_net_6));
+MUX2 
+    synth_MUX_0(.in({synth_net_1, synth_net_4}), .select(cond), .out(synth_net_7
+    ));
+FF synth_FF(.d(synth_net_11), .clk(clk), .q(data));
+VCC synth_VCC(.out(
+    synth_net));
+VCC synth_VCC_0(.out(synth_net_1));
+VCC synth_VCC_1(.out(
+    synth_net_4));
+VCC synth_VCC_2(.out(synth_net_10));
+endmodule
+
diff --git a/tests/hana/test_simulation_xnor.v b/tests/hana/test_simulation_xnor.v
new file mode 100644
index 00000000..7286d134
--- /dev/null
+++ b/tests/hana/test_simulation_xnor.v
@@ -0,0 +1,20 @@
+
+// test_simulation_xnor_1_test.v
+module f1_test(input [1:0] in, output out);
+assign out = ~(in[0] ^ in[1]);
+endmodule
+
+// test_simulation_xnor_2_test.v
+module f2_test(input [2:0] in, output out);
+assign out = ~(in[0] ^ in[1] ^ in[2]);
+endmodule
+
+// test_simulation_xnor_3_test.v
+module f3_test(input [3:0] in, output out);
+assign out = ~(in[0] ^ in[1] ^ in[2] ^ in[3]);
+endmodule
+
+// test_simulation_xnor_4_test.v
+module f4_test(input [3:0] in, output out);
+xnor myxnor(out, in[0], in[1], in[2], in[3]);
+endmodule
diff --git a/tests/hana/test_simulation_xnor_1_test.v b/tests/hana/test_simulation_xnor_1_test.v
deleted file mode 100644
index adc6ae5c..00000000
--- a/tests/hana/test_simulation_xnor_1_test.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module test(input [1:0] in, output out);
-assign out = ~(in[0] ^ in[1]);
-endmodule
diff --git a/tests/hana/test_simulation_xnor_2_test.v b/tests/hana/test_simulation_xnor_2_test.v
deleted file mode 100644
index 701bcc77..00000000
--- a/tests/hana/test_simulation_xnor_2_test.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module test(input [2:0] in, output out);
-assign out = ~(in[0] ^ in[1] ^ in[2]);
-endmodule
diff --git a/tests/hana/test_simulation_xnor_3_test.v b/tests/hana/test_simulation_xnor_3_test.v
deleted file mode 100644
index a8c87cc6..00000000
--- a/tests/hana/test_simulation_xnor_3_test.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module test(input [3:0] in, output out);
-assign out = ~(in[0] ^ in[1] ^ in[2] ^ in[3]);
-endmodule
diff --git a/tests/hana/test_simulation_xnor_4_test.v b/tests/hana/test_simulation_xnor_4_test.v
deleted file mode 100644
index fa671ff9..00000000
--- a/tests/hana/test_simulation_xnor_4_test.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module test(input [3:0] in, output out);
-xnor myxnor(out, in[0], in[1], in[2], in[3]);
-endmodule
diff --git a/tests/hana/test_simulation_xor.v b/tests/hana/test_simulation_xor.v
new file mode 100644
index 00000000..e181dd83
--- /dev/null
+++ b/tests/hana/test_simulation_xor.v
@@ -0,0 +1,20 @@
+
+// test_simulation_xor_1_test.v
+module f1_test(input [1:0] in, output out);
+assign out = (in[0] ^ in[1]);
+endmodule
+
+// test_simulation_xor_2_test.v
+module f2_test(input [2:0] in, output out);
+assign out = (in[0] ^ in[1] ^ in[2]);
+endmodule
+
+// test_simulation_xor_3_test.v
+module f3_test(input [3:0] in, output out);
+assign out = (in[0] ^ in[1] ^ in[2] ^ in[3]);
+endmodule
+
+// test_simulation_xor_4_test.v
+module f4_test(input [3:0] in, output out);
+xor myxor(out, in[0], in[1], in[2], in[3]);
+endmodule
diff --git a/tests/hana/test_simulation_xor_1_test.v b/tests/hana/test_simulation_xor_1_test.v
deleted file mode 100644
index f6447f81..00000000
--- a/tests/hana/test_simulation_xor_1_test.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module test(input [1:0] in, output out);
-assign out = (in[0] ^ in[1]);
-endmodule
diff --git a/tests/hana/test_simulation_xor_2_test.v b/tests/hana/test_simulation_xor_2_test.v
deleted file mode 100644
index d94081df..00000000
--- a/tests/hana/test_simulation_xor_2_test.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module test(input [2:0] in, output out);
-assign out = (in[0] ^ in[1] ^ in[2]);
-endmodule
diff --git a/tests/hana/test_simulation_xor_3_test.v b/tests/hana/test_simulation_xor_3_test.v
deleted file mode 100644
index cfa13187..00000000
--- a/tests/hana/test_simulation_xor_3_test.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module test(input [3:0] in, output out);
-assign out = (in[0] ^ in[1] ^ in[2] ^ in[3]);
-endmodule
diff --git a/tests/hana/test_simulation_xor_4_test.v b/tests/hana/test_simulation_xor_4_test.v
deleted file mode 100644
index be6cab63..00000000
--- a/tests/hana/test_simulation_xor_4_test.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module test(input [3:0] in, output out);
-xor myxor(out, in[0], in[1], in[2], in[3]);
-endmodule
-- 
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