/-----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \-----------------------------------------------------------------------------/ yosys -- Yosys Open SYnthesis Suite =================================== This is a framework for RTL synthesis tools. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains. Yosys can be adapted to perform any synthesis job by combining the existing passes (algorithms) using synthesis scripts and adding additional passes as needed by extending the yosys C++ code base. Yosys is free software licensed under the ISC license (a GPL compatible license that is similar in terms to the MIT license or the 2-clause BSD license). Web Site ======== More information and documentation can be found on the Yosys web site: http://www.clifford.at/yosys/ Getting Started =============== You need a C++ compiler with C++11 support (up-to-date CLANG or GCC is recommended) and some standard tools such as GNU Flex, GNU Bison, and GNU Make. The Qt4 library is needed for the yosys SVG viewer, that is used to display schematics, the minisat library is required for the SAT features in yosys and TCL for the scripting functionality. The extensive test suite requires Icarus Verilog. For example on Ubuntu Linux 12.04 LTS the following commands will install all prerequisites for building yosys: $ sudo apt-get install git $ sudo apt-get install g++ $ sudo apt-get install clang $ sudo apt-get install make $ sudo apt-get install bison $ sudo apt-get install flex $ sudo apt-get install libreadline-dev $ sudo apt-get install tcl8.5-dev $ sudo apt-get install minisat $ sudo apt-get install zlib1g-dev $ sudo apt-get install libqt4-dev $ sudo apt-get install mercurial $ sudo apt-get install iverilog $ sudo apt-get install graphviz To configure the build system to use a specific set of compiler and build configuration, use one of $ make config-clang-debug $ make config-gcc-debug $ make config-release For other compilers and build configurations it might be necessary to make some changes to the config section of the Makefile. $ vi Makefile To build Yosys simply type 'make' in this directory. $ make $ make test $ sudo make install If you encounter any problems during build, make sure to check the section "Workarounds for known build problems" at the end of this README file. Note that this also downloads, builds and installs ABC (using yosys-abc as executeable name). Yosys can be used with the interactive command shell, with synthesis scripts or with command line arguments. Let's perform a simple synthesis job using the interactive command shell: $ ./yosys yosys> the command "help" can be used to print a list of all available commands and "help " to print details on the specified command: yosys> help help reading the design using the verilog frontend: yosys> read_verilog tests/simple/fiedler-cooley.v writing the design to the console in yosys's internal format: yosys> write_ilang convert processes ("always" blocks) to netlist elements and perform some simple optimizations: yosys> proc; opt display design netlist using the yosys svg viewer: yosys> show the same thing using 'gv' as postscript viewer: yosys> show -format ps -viewer gv translating netlist to gate logic and perform some simple optimizations: yosys> techmap; opt write design netlist to a new verilog file: yosys> write_verilog synth.v a similar synthesis can be performed using yosys command line options only: $ ./yosys -o synth.v -p proc -p opt -p techmap -p opt tests/simple/fiedler-cooley.v or using a simple synthesis script: $ cat synth.ys read_verilog tests/simple/fiedler-cooley.v proc; opt; techmap; opt write_verilog synth.v $ ./yosys synth.ys It is also possible to only have the synthesis commands but not the read/write commands in the synthesis script: $ cat synth.ys proc; opt; techmap; opt $ ./yosys -o synth.v tests/simple/fiedler-cooley.v synth.ys The following synthesis script works reasonable for all designs: # check design hierarchy hierarchy # translate processes (always blocks) and memories (arrays) proc; memory; opt # detect and optimize FSM encodings fsm; opt # convert to gate logic techmap; opt If ABC is enabled in the Yosys build configuration and a cell library is given in the liberty file mycells.lib, the following synthesis script will synthesize for the given cell library: # the high-level stuff hierarchy; proc; memory; opt; fsm; opt # mapping to internal cell library techmap; opt # mapping flip-flops to mycells.lib dfflibmap -liberty mycells.lib # mapping logic to mycells.lib abc -liberty mycells.lib # cleanup clean If you do not have a liberty file but want to test this synthesis script, you can use the file techlibs/cmos/cmos_cells.lib from the yosys sources. Yosys is under construction. A more detailed documentation will follow. Unsupported Verilog-2005 Features ================================= The following Verilog-2005 features are not supported by yosys and there are currently no plans to add support for them: - Non-sythesizable language features as defined in IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002 - The "tri", "triand", "trior", "wand" and "wor" net types - The "config" keyword and library map files - The "disable", "primitive" and "specify" statements - Latched logic (is synthesized as logic with feedback loops) Verilog Attributes and non-standard features ============================================ - The 'full_case' attribute on case statements is supported (also the non-standard "// synopsys full_case" directive) - The 'parallel_case' attribute on case statements is supported (also the non-standard "// synopsys parallel_case" directive) - The "// synopsys translate_off" and "// synopsys translate_on" directives are also supported (but the use of `ifdef .. `endif is strongly recommended instead). - The "nomem2reg" attribute on modules or arrays prohibits the automatic early conversion of arrays to separate registers. - The "mem2reg" attribute on modules or arrays forces the early conversion of arrays to separate registers. - The "nolatches" attribute on modules or always-blocks prohibits the generation of logic-loops for latches. Instead all not explicitly assigned values default to x-bits. This does not affect clocked storage elements such as flip-flops. - The "nosync" attribute on registers prohibits the generation of a storage element. The register itself will always have all bits set to 'x' (undefined). The variable may only be used as blocking assigned temporary variable within an always block. This is mostly used internally by yosys to synthesize verilog functions and access arrays. - The "blackbox" attribute on modules is used to mark empty stub modules that have the same ports as the real thing but do not contain information on the internal configuration. This modules are only used by the synthesis passes to identify input and output ports of cells. The verilog backend also does not output blackbox modules on default. - The "keep" attribute on cells and wires is used to mark objects that should never be removed by the optimizer. This is used for example for cells that have hidden connections that are not part of the netlist, such as IO pads. - The "init" attribute on wires is set by the frontend when a register is initialized "FPGA-style" with 'reg foo = val'. It can be used during synthesis to add the necessary reset logic. - The "top" attribute on a module marks this module as the top of the design hierarchy. The "hierarchy" command sets this attribute when called with "-top". Other commands, such as "flatten" and various backends use this attribute to determine the top module. - In addition to the (* ... *) attribute syntax, yosys supports the non-standard {* ... *} attribute syntax to set default attributes for everything that comes after the {* ... *} statement. (Reset by adding an empty {* *} statement.) - The "assert" statement from SystemVerilog is supported in its most basic form. In module context: "assert property ();" and within an always block: "assert();". It is transformed to a $assert cell that is supported by the "sat" and "write_btor" commands. - Sized constants (the syntax 's?[bodh]) support constant expressions as . If the expresion is not a simple identifier, it must be put in parentheses. Examples: WIDTH'd42, (4+2)'b101010 Workarounds for known build problems ==================================== You might get an error message like this one during build when building with a recent version of gcc: /usr/include/minisat/utils/Options.h:285:29: error: unable to find string literal operator ‘operator"" PRIi64’ This is a bug in the minisat header. It can be fixed by adding spaces before and after each occurrence of PRIi64 in the header file: sudo sed -i 's/PRIi64/ & /' /usr/include/minisat/utils/Options.h Roadmap / Large-scale TODOs =========================== - Verification and Regression Tests - VlogHammer: http://www.clifford.at/yosys/vloghammer.html - yosys-bigsim: https://github.com/cliffordwolf/yosys-bigsim - Technology mapping for real-world applications - Add bit-wise const-folding via cell parameters to techmap pass - Rewrite current stdcells.v techmap rules (modular and clean) - Improve Xilinx FGPA synthesis (RAMB, CARRY4, SLR, etc.) - Implement SAT-based formal equivialence checker - Write equiv pass based on hint-based register mapping - Re-implement Verilog frontend (far future) - cleaner (easier to use, harder to use wrong) AST format - pipeline of well structured AST transformations - true contextual name lookup Other Unsorted TODOs ==================== - Implement missing Verilog 2005 features: - Multi-dimensional arrays - Support for real (float) const. expressions and parameters - ROM modeling using $readmemh/$readmemb in "initial" blocks - Ignore what needs to be ignored (e.g. drive and charge strengths) - Check standard vs. implementation to identify missing features - Miscellaneous TODO items: - Add brief source code documentation to most passes and kernel code - Implement mux-to-tribuf pass and rebalance mixed mux/tribuf trees - Add more commands for changing the design (delete, add, modify objects) - Add full support for $lut cell type (const evaluation, sat solving, etc.) - Smarter resource sharing pass (add MUXes and get rid of duplicated cells)