Source: yosys
Section: electronics
Priority: optional
Maintainer: Ruben Undheim <ruben.undheim@gmail.com>
Build-Depends: debhelper (>= 9), tcl8.5-dev, libreadline-dev, git, bison,
               flex, gawk, libffi-dev
Standards-Version: 3.9.5
Vcs-Git: git://github.com/rubund/yosys.git -b debian
Vcs-Browser: https://github.com/rubund/yosys/tree/debian
Homepage: http://www.clifford.at/yosys

Package: yosys
Architecture: any
Depends: ${shlibs:Depends}, ${misc:Depends}, iverilog, graphviz, xdot,
         berkeley-abc
Description: Framework for Verilog RTL synthesis
 This is a framework for Verilog RTL synthesis. It currently has extensive
 Verilog-2005 support and provides a basic set of synthesis algorithms for
 various application domains.
 .
 Yosys can be adapted to perform any synthesis job by combining the existing
 passes (algorithms) using synthesis scripts and adding additional passes as
 needed by extending the yosys C++ code base.