bram $__XILINX_RAMB36_SDP72
  abits 9
  dbits 72
  groups 2
  ports  1 1
  wrmode 0 1
  enable 0 8
  transp 2 0
  clocks 2 3
  clkpol 2 3
endbram

bram $__XILINX_RAMB18_SDP36
  abits 9
  dbits 36
  groups 2
  ports  1 1
  wrmode 0 1
  enable 0 4
  transp 2 0
  clocks 2 3
  clkpol 2 3
endbram

bram $__XILINX_RAMB18_TDP18
  abits 10
  dbits 18
  groups 2
  ports  1 1
  wrmode 0 1
  enable 0 2
  transp 2 0
  clocks 2 3
  clkpol 2 3
endbram

bram $__XILINX_RAMB18_TDP9
  abits 11
  dbits 9
  groups 2
  ports  1 1
  wrmode 0 1
  enable 0 1
  transp 2 0
  clocks 2 3
  clkpol 2 3
endbram

bram $__XILINX_RAMB18_TDP4
  abits 12
  dbits 4
  groups 2
  ports  1 1
  wrmode 0 1
  enable 0 1
  transp 2 0
  clocks 2 3
  clkpol 2 3
endbram

bram $__XILINX_RAMB18_TDP2
  abits 13
  dbits 2
  groups 2
  ports  1 1
  wrmode 0 1
  enable 0 1
  transp 2 0
  clocks 2 3
  clkpol 2 3
endbram

bram $__XILINX_RAMB18_TDP1
  abits 14
  dbits 1
  groups 2
  ports  1 1
  wrmode 0 1
  enable 0 1
  transp 2 0
  clocks 2 3
  clkpol 2 3
endbram

match $__XILINX_RAMB36_SDP72
  min bits 4096
  min efficiency 5
  shuffle_enable 8
  or_next_if_better
endmatch

match $__XILINX_RAMB18_SDP36
  min bits 4096
  min efficiency 5
  shuffle_enable 4
  or_next_if_better
endmatch

match $__XILINX_RAMB18_TDP18
  min bits 4096
  min efficiency 5
  shuffle_enable 2
  or_next_if_better
endmatch
 
match $__XILINX_RAMB18_TDP9
  min bits 4096
  min efficiency 5
  shuffle_enable 2
  or_next_if_better
endmatch

match $__XILINX_RAMB18_TDP4
  min bits 4096
  min efficiency 5
  shuffle_enable 2
  or_next_if_better
endmatch

match $__XILINX_RAMB18_TDP2
  min bits 4096
  min efficiency 5
  shuffle_enable 2
  or_next_if_better
endmatch

match $__XILINX_RAMB18_TDP1
  min bits 4096
  min efficiency 5
  shuffle_enable 2
endmatch