///////////////////////////////////////////////////////////////////// //// //// //// FPU //// //// Floating Point Unit (Single precision) //// //// //// //// Author: Rudolf Usselmann //// //// rudi@asics.ws //// //// //// ///////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Rudolf Usselmann //// //// rudi@asics.ws //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer.//// //// //// //// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// //// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// //// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// //// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// //// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// //// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// //// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// //// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// //// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// //// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// //// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// //// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// //// POSSIBILITY OF SUCH DAMAGE. //// //// //// ///////////////////////////////////////////////////////////////////// `timescale 1ns / 100ps /* FPU Operations (fpu_op): ======================== 0 = add 1 = sub 2 = mul 3 = div 4 = 5 = 6 = 7 = Rounding Modes (rmode): ======================= 0 = round_nearest_even 1 = round_to_zero 2 = round_up 3 = round_down */ module fpu( clk, rmode, fpu_op, opa, opb, out, inf, snan, qnan, ine, overflow, underflow, zero, div_by_zero); input clk; input [1:0] rmode; input [2:0] fpu_op; input [31:0] opa, opb; output [31:0] out; output inf, snan, qnan; output ine; output overflow, underflow; output zero; output div_by_zero; parameter INF = 31'h7f800000, QNAN = 31'h7fc00001, SNAN = 31'h7f800001; //////////////////////////////////////////////////////////////////////// // // Local Wires // reg zero; reg [31:0] opa_r, opb_r; // Input operand registers reg [31:0] out; // Output register reg div_by_zero; // Divide by zero output register wire signa, signb; // alias to opX sign wire sign_fasu; // sign output wire [26:0] fracta, fractb; // Fraction Outputs from EQU block wire [7:0] exp_fasu; // Exponent output from EQU block reg [7:0] exp_r; // Exponent output (registerd) wire [26:0] fract_out_d; // fraction output wire co; // carry output reg [27:0] fract_out_q; // fraction output (registerd) wire [30:0] out_d; // Intermediate final result output wire overflow_d, underflow_d;// Overflow/Underflow Indicators reg overflow, underflow; // Output registers for Overflow & Underflow reg inf, snan, qnan; // Output Registers for INF, SNAN and QNAN reg ine; // Output Registers for INE reg [1:0] rmode_r1, rmode_r2, // Pipeline registers for rounding mode rmode_r3; reg [2:0] fpu_op_r1, fpu_op_r2, // Pipeline registers for fp opration fpu_op_r3; wire mul_inf, div_inf; wire mul_00, div_00; //////////////////////////////////////////////////////////////////////// // // Input Registers // always @(posedge clk) opa_r <= #1 opa; always @(posedge clk) opb_r <= #1 opb; always @(posedge clk) rmode_r1 <= #1 rmode; always @(posedge clk) rmode_r2 <= #1 rmode_r1; always @(posedge clk) rmode_r3 <= #1 rmode_r2; always @(posedge clk) fpu_op_r1 <= #1 fpu_op; always @(posedge clk) fpu_op_r2 <= #1 fpu_op_r1; always @(posedge clk) fpu_op_r3 <= #1 fpu_op_r2; //////////////////////////////////////////////////////////////////////// // // Exceptions block // wire inf_d, ind_d, qnan_d, snan_d, opa_nan, opb_nan; wire opa_00, opb_00; wire opa_inf, opb_inf; wire opa_dn, opb_dn; except u0( .clk(clk), .opa(opa_r), .opb(opb_r), .inf(inf_d), .ind(ind_d), .qnan(qnan_d), .snan(snan_d), .opa_nan(opa_nan), .opb_nan(opb_nan), .opa_00(opa_00), .opb_00(opb_00), .opa_inf(opa_inf), .opb_inf(opb_inf), .opa_dn(opa_dn), .opb_dn(opb_dn) ); //////////////////////////////////////////////////////////////////////// // // Pre-Normalize block // - Adjusts the numbers to equal exponents and sorts them // - determine result sign // - determine actual operation to perform (add or sub) // wire nan_sign_d, result_zero_sign_d; reg sign_fasu_r; wire [7:0] exp_mul; wire sign_mul; reg sign_mul_r; wire [23:0] fracta_mul, fractb_mul; wire inf_mul; reg inf_mul_r; wire [1:0] exp_ovf; reg [1:0] exp_ovf_r; wire sign_exe; reg sign_exe_r; wire [2:0] underflow_fmul_d; pre_norm u1(.clk(clk), // System Clock .rmode(rmode_r2), // Roundin Mode .add(!fpu_op_r1[0]), // Add/Sub Input .opa(opa_r), .opb(opb_r), // Registered OP Inputs .opa_nan(opa_nan), // OpA is a NAN indicator .opb_nan(opb_nan), // OpB is a NAN indicator .fracta_out(fracta), // Equalized and sorted fraction .fractb_out(fractb), // outputs (Registered) .exp_dn_out(exp_fasu), // Selected exponent output (registered); .sign(sign_fasu), // Encoded output Sign (registered) .nan_sign(nan_sign_d), // Output Sign for NANs (registered) .result_zero_sign(result_zero_sign_d), // Output Sign for zero result (registered) .fasu_op(fasu_op) // Actual fasu operation output (registered) ); always @(posedge clk) sign_fasu_r <= #1 sign_fasu; pre_norm_fmul u2( .clk(clk), .fpu_op(fpu_op_r1), .opa(opa_r), .opb(opb_r), .fracta(fracta_mul), .fractb(fractb_mul), .exp_out(exp_mul), // FMUL exponent output (registered) .sign(sign_mul), // FMUL sign output (registered) .sign_exe(sign_exe), // FMUL exception sign output (registered) .inf(inf_mul), // FMUL inf output (registered) .exp_ovf(exp_ovf), // FMUL exponnent overflow output (registered) .underflow(underflow_fmul_d) ); always @(posedge clk) sign_mul_r <= #1 sign_mul; always @(posedge clk) sign_exe_r <= #1 sign_exe; always @(posedge clk) inf_mul_r <= #1 inf_mul; always @(posedge clk) exp_ovf_r <= #1 exp_ovf; //////////////////////////////////////////////////////////////////////// // // Add/Sub // add_sub27 u3( .add(fasu_op), // Add/Sub .opa(fracta), // Fraction A input .opb(fractb), // Fraction B Input .sum(fract_out_d), // SUM output .co(co_d) ); // Carry Output always @(posedge clk) fract_out_q <= #1 {co_d, fract_out_d}; //////////////////////////////////////////////////////////////////////// // // Mul // wire [47:0] prod; mul_r2 u5(.clk(clk), .opa(fracta_mul), .opb(fractb_mul), .prod(prod)); //////////////////////////////////////////////////////////////////////// // // Divide // wire [49:0] quo; wire [49:0] fdiv_opa; wire [49:0] remainder; wire remainder_00; reg [4:0] div_opa_ldz_d, div_opa_ldz_r1, div_opa_ldz_r2; always @(fracta_mul) casex(fracta_mul[22:0]) 23'b1??????????????????????: div_opa_ldz_d = 1; 23'b01?????????????????????: div_opa_ldz_d = 2; 23'b001????????????????????: div_opa_ldz_d = 3; 23'b0001???????????????????: div_opa_ldz_d = 4; 23'b00001??????????????????: div_opa_ldz_d = 5; 23'b000001?????????????????: div_opa_ldz_d = 6; 23'b0000001????????????????: div_opa_ldz_d = 7; 23'b00000001???????????????: div_opa_ldz_d = 8; 23'b000000001??????????????: div_opa_ldz_d = 9; 23'b0000000001?????????????: div_opa_ldz_d = 10; 23'b00000000001????????????: div_opa_ldz_d = 11; 23'b000000000001???????????: div_opa_ldz_d = 12; 23'b0000000000001??????????: div_opa_ldz_d = 13; 23'b00000000000001?????????: div_opa_ldz_d = 14; 23'b000000000000001????????: div_opa_ldz_d = 15; 23'b0000000000000001???????: div_opa_ldz_d = 16; 23'b00000000000000001??????: div_opa_ldz_d = 17; 23'b000000000000000001?????: div_opa_ldz_d = 18; 23'b0000000000000000001????: div_opa_ldz_d = 19; 23'b00000000000000000001???: div_opa_ldz_d = 20; 23'b000000000000000000001??: div_opa_ldz_d = 21; 23'b0000000000000000000001?: div_opa_ldz_d = 22; 23'b0000000000000000000000?: div_opa_ldz_d = 23; endcase assign fdiv_opa = !(|opa_r[30:23]) ? {(fracta_mul<