blob: 896d4300ff511bccad76061fadef9584f1bfee37 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
|
Source: yosys
Maintainer: Debian Science Maintainers <debian-science-maintainers@lists.alioth.debian.org>
Uploaders: Ruben Undheim <ruben.undheim@gmail.com>
Section: electronics
Priority: optional
Build-Depends: debhelper (>= 9),
tcl8.5-dev,
libreadline-dev,
bison,
flex,
gawk,
libffi-dev,
pkg-config
Standards-Version: 3.9.6
Vcs-Browser: https://anonscm.debian.org/cgit/debian-science/packages/yosys.git
Vcs-Git: git://anonscm.debian.org/debian-science/packages/yosys.git
Homepage: http://www.clifford.at/yosys
Package: yosys
Architecture: any
Depends: ${shlibs:Depends},
${misc:Depends},
berkeley-abc (>= 1.01),
xdot
Description: Framework for Verilog RTL synthesis
This is a framework for Verilog RTL synthesis. It currently has extensive
Verilog-2005 support and provides a basic set of synthesis algorithms for
various application domains.
.
Yosys can be adapted to perform any synthesis job by combining the existing
passes (algorithms) using synthesis scripts and adding additional passes as
needed by extending the yosys C++ code base.
|
