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Source: yosys
Maintainer: Debian Science Maintainers <debian-science-maintainers@lists.alioth.debian.org>
Uploaders: Ruben Undheim <ruben.undheim@gmail.com>,
Sebastian Kuzminsky <seb@highlab.com>
Section: electronics
Priority: optional
Build-Depends: debhelper-compat (= 12),
dh-python,
tcl-dev,
libreadline-dev,
bison,
flex,
gawk,
libffi-dev,
pkg-config,
txt2man,
iverilog (>= 10.1),
python3,
berkeley-abc (>= 1.01+20161002hgeb6eca6+dfsg)
Build-Depends-Indep:
texlive-base,
texlive-plain-generic,
texlive-fonts-recommended,
texlive-fonts-extra,
texlive-latex-base,
texlive-latex-extra,
texlive-font-utils,
texlive-science,
texlive-publishers,
texlive-bibtex-extra,
lmodern,
graphviz
Standards-Version: 4.4.0
Vcs-Browser: https://salsa.debian.org/science-team/yosys
Vcs-Git: https://salsa.debian.org/science-team/yosys.git
Homepage: http://www.clifford.at/yosys
Package: yosys
Architecture: any
Depends: ${shlibs:Depends},
${python3:Depends},
${misc:Depends},
berkeley-abc (>= 1.01+20161002hgeb6eca6+dfsg),
xdot
Description: Framework for Verilog RTL synthesis
This is a framework for Verilog RTL synthesis. It currently has extensive
Verilog-2005 support and provides a basic set of synthesis algorithms for
various application domains.
.
Yosys can be adapted to perform any synthesis job by combining the existing
passes (algorithms) using synthesis scripts and adding additional passes as
needed by extending the yosys C++ code base.
Package: yosys-dev
Architecture: any
Depends: ${shlibs:Depends},
${python3:Depends},
${misc:Depends}
Description: Framework for Verilog RTL synthesis (development files)
Yosys is a framework for Verilog RTL synthesis. It currently has extensive
Verilog-2005 support and provides a basic set of synthesis algorithms for
various application domains.
.
Yosys can be adapted to perform any synthesis job by combining the existing
passes (algorithms) using synthesis scripts and adding additional passes as
needed by extending the yosys C++ code base.
.
This package contains the headers and programs needed to build yosys plugins.
Package: yosys-doc
Section: doc
Architecture: all
Depends: ${misc:Depends}
Multi-Arch: foreign
Suggests: yosys
Description: Documentation for Yosys
Yosys is a framework for Verilog RTL synthesis. It currently has extensive
Verilog-2005 support and provides a basic set of synthesis algorithms for
various application domains.
.
Yosys can be adapted to perform any synthesis job by combining the existing
passes (algorithms) using synthesis scripts and adding additional passes as
needed by extending the yosys C++ code base.
.
This package contains the manual.
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