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From: Ruben Undheim <ruben.undheim@gmail.com>
Date: Thu, 12 Jul 2018 13:41:39 +0200
Subject: Some spelling errors fixed

---
 backends/simplec/simplec.cc         | 2 +-
 backends/table/table.cc             | 2 +-
 backends/verilog/verilog_backend.cc | 2 +-
 frontends/blif/blifparse.cc         | 2 +-
 frontends/liberty/liberty.cc        | 2 +-
 manual/CHAPTER_Overview.tex         | 2 +-
 manual/command-reference-manual.tex | 2 +-
 passes/cmds/show.cc                 | 2 +-
 8 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/backends/simplec/simplec.cc b/backends/simplec/simplec.cc
index 349bc5a..6f2ccbe 100644
--- a/backends/simplec/simplec.cc
+++ b/backends/simplec/simplec.cc
@@ -748,7 +748,7 @@ struct SimplecBackend : public Backend {
 		log("\n");
 		log("    write_simplec [options] [filename]\n");
 		log("\n");
-		log("Write simple C code for simulating the design. The C code writen can be used to\n");
+		log("Write simple C code for simulating the design. The C code written can be used to\n");
 		log("simulate the design in a C environment, but the purpose of this command is to\n");
 		log("generate code that works well with C-based formal verification.\n");
 		log("\n");
diff --git a/backends/table/table.cc b/backends/table/table.cc
index 979273d..b75169e 100644
--- a/backends/table/table.cc
+++ b/backends/table/table.cc
@@ -109,7 +109,7 @@ struct TableBackend : public Backend {
 				else if (cell->output(conn.first))
 					*f << "out" << "\t";
 				else
-					*f << "unkown" << "\t";
+					*f << "unknown" << "\t";
 
 				*f << log_signal(sigmap(conn.second)) << "\n";
 			}
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index ae90315..d53df2e 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1415,7 +1415,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
 		}
 
 	if (!module->processes.empty())
-		log_warning("Module %s contains unmapped RTLIL proccesses. RTLIL processes\n"
+		log_warning("Module %s contains unmapped RTLIL processes. RTLIL processes\n"
 				"can't always be mapped directly to Verilog always blocks. Unintended\n"
 				"changes in simulation behavior are possible! Use \"proc\" to convert\n"
 				"processes to logic networks and registers.", log_id(module));
diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc
index 034b3e7..9116b25 100644
--- a/frontends/blif/blifparse.cc
+++ b/frontends/blif/blifparse.cc
@@ -276,7 +276,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo
 
 				if(lastcell == nullptr || module == nullptr)
 				{
-					err_reason = stringf("No primative object to attach .cname %s.", p);
+					err_reason = stringf("No primitive object to attach .cname %s.", p);
 					goto error_with_reason;
 				}
 
diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc
index 0a5bd84..e90c87a 100644
--- a/frontends/liberty/liberty.cc
+++ b/frontends/liberty/liberty.cc
@@ -615,7 +615,7 @@ struct LibertyFrontend : public Frontend {
 					LibertyAst *bus_type_node = node->find("bus_type");
 
 					if (!bus_type_node || !type_map.count(bus_type_node->value))
-						log_error("Unkown or unsupported type for bus interface %s on cell %s.\n",
+						log_error("Unknown or unsupported type for bus interface %s on cell %s.\n",
 								node->args.at(0).c_str(), log_id(cell_name));
 
 					int bus_type_width = std::get<0>(type_map.at(bus_type_node->value));
diff --git a/manual/CHAPTER_Overview.tex b/manual/CHAPTER_Overview.tex
index 964875d..ae5cf09 100644
--- a/manual/CHAPTER_Overview.tex
+++ b/manual/CHAPTER_Overview.tex
@@ -240,7 +240,7 @@ An RTLIL::Wire object has the following properties:
 As with modules, the attributes can be Verilog attributes imported by the
 Verilog frontend or attributes assigned by passes.
 
-In Yosys, busses (signal vectors) are represented using a single wire object
+In Yosys, buses (signal vectors) are represented using a single wire object
 with a width > 1. So Yosys does not convert signal vectors to individual signals.
 This makes some aspects of RTLIL more complex but enables Yosys to be used for
 coarse grain synthesis where the cells of the target architecture operate on
diff --git a/manual/command-reference-manual.tex b/manual/command-reference-manual.tex
index fea2354..c530186 100644
--- a/manual/command-reference-manual.tex
+++ b/manual/command-reference-manual.tex
@@ -2859,7 +2859,7 @@ to a graphics file (usually SVG or PostScript).
         assigned to each unique value of this attribute.
 
     -width
-        annotate busses with a label indicating the width of the bus.
+        annotate buses with a label indicating the width of the bus.
 
     -signed
         mark ports (A, B) that are declared as signed (using the [AB]_SIGNED
diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc
index a488732..58acd30 100644
--- a/passes/cmds/show.cc
+++ b/passes/cmds/show.cc
@@ -623,7 +623,7 @@ struct ShowPass : public Pass {
 		log("        assigned to each unique value of this attribute.\n");
 		log("\n");
 		log("    -width\n");
-		log("        annotate busses with a label indicating the width of the bus.\n");
+		log("        annotate buses with a label indicating the width of the bus.\n");
 		log("\n");
 		log("    -signed\n");
 		log("        mark ports (A, B) that are declared as signed (using the [AB]_SIGNED\n");